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Programmable Capacitance-to-Digital Converter with Environmental Compensation
Preliminary Technical Data
FEATURES
Programmable capacitance-to-digital converter 30 Hz update rate (@ maximum sequence length) Better than one femto Farad resolution 14 capacitance sensor input channels No external RC tuning components required Automatic conversion sequencer On-chip automatic calibration logic Automatic compensation for environmental changes Automatic adaptive threshold and sensitivity levels On-chip RAM to store calibration data SPI(R)- or I2C(R)- (AD7142-1) compatible serial interface Separate VDRIVE level for serial interface Interrupt output and GPIO 32-lead, 5 mm x 5 mm LFCSP 2.7 V to 3.3 V supply voltage Low operating current Full power mode: less than1 mA Low power mode: 50 A
AD7142/AD7142-1
FUNCTIONAL BLOCK DIAGRAM
VREF- VREF+
29 28
TEST
27
CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN11 CIN12 CIN13
30 31 32 1
POWER-ON RESET LOGIC AVCC AGND
13 2 3 14
SWITCH MATRIX
4 5 6 7 8 9 10 11
16-BIT - CDC
CALIBRATION ENGINE
17
DVCC DGND1 DGND2
AD7142
CONTROL AND DATA REGISTERS
CALIBRATION RAM
18
19
CSHIELD
12
SRC SRC
15 16
240kHz EXCITATION SOURCE
VDRIVE
20
SERIAL INTERFACE AND CONTROL LOGIC
APPLICATIONS
Personal music and multimedia players Cell phones Digital still cameras Smart hand-held devices Television, A/V and remote controls Gaming consoles
21 22 23 24
INTERRUPT AND GPIO LOGIC
26 GPIO
25
SDO/ SDA
SDI/ SCLK CS/ ADD1 ADD0
INT
Figure 1.
GENERAL DESCRIPTION
The AD7142 and AD7142-1 are integrated capacitance-todigital converters (CDCs) with on-chip environmental calibration for use in systems requiring a novel user input method. The AD7142 and AD7142-1 can interface to external capacitance sensors implementing functions such as capacitive buttons, scroll bars, or joypads. The CDC has 14 inputs, channeled through a switch matrix to a 16-bit, 240 kHz sigma-delta (-) capacitance-to-digital converter. The CDC is capable of sensing changes in the capacitance of the external sensors and uses this information to register a sensor activation. The external sensors can be arranged as a series of buttons, as a scroll bar or wheel, or as a combination of sensor types. By programming the registers, the user has full control over the CDC setup. High resolution scroll bar sensors require software to run on the host processor. The AD7142 and AD7142-1 have on-chip calibration logic to account for changes in the ambient environment. The calibration sequence is performed automatically and at continuous intervals, while the sensors are not touched. This ensures that there are no false or nonregistering touches on the external sensors due to a changing environment. The AD7142 has an SPI-compatible serial interface, and the AD7142-1 has an I2C-compatible serial interface. Both versions of AD7142 have an interrupt output, as well as a general-purpose input output (GPIO). The AD7142 and AD7142-1 are available in a 32-lead, 5 mm x 5 mm LFCSP package and operate from a 2.7 V to 3.3 V supply. The operating current consumption is less than 1 mA, falling to 50 A in low power mode (conversion interval of 400 ms).
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05702-001
AD7142/AD7142-1 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 SPI Timing Specifications AD7142............................................ 4 I2C Timing Specifications AD7142-1 ........................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Functional Descriptions......................... 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ........................................................................ 9 Capacitance Sensing Theory....................................................... 9 Operating Modes........................................................................ 10 Capacitance Sensor Input Configuration.................................... 11 CIN Input Multiplexer Setup .................................................... 11 Capacitiance-to-Digital Converter............................................... 12 Oversampling the CDC Output ............................................... 12 Capacitance Sensor Offset Control.......................................... 12 Conversion Sequencer ............................................................... 12 CDC Conversion Time.............................................................. 13 CDC Conversion Results........................................................... 14 Non-Contact Proximity Detection............................................... 15 Environmental Calibration ........................................................... 19
Preliminary Technical Data
Adaptive Threshold and Sensitivity ............................................. 20 Interrupt Output............................................................................. 21 CDC Conversion Complete Interrupt..................................... 21 Sensor Threshold Interrupt ...................................................... 21 GPIO INT Output Control ....................................................... 22 Outputs ............................................................................................ 24 Excitation Source........................................................................ 24 CSHIELD Output ............................................................................. 24 GPIO ............................................................................................ 24 Serial Interface ................................................................................ 25 SPI Interface ................................................................................ 25 I2C Interface ................................................................................ 27 VDRIVE Input ................................................................................. 29 PCB Design Guidelines ................................................................. 30 Capacitive Sensor Board Mechanical Specifications ............. 30 Chip Scale Packages ................................................................... 30 Power-Up Sequence ....................................................................... 31 Typical Application Circuits ......................................................... 32 Register Map ................................................................................... 33 Detailed Register Descriptions ..................................................... 34 Bank 1 Registers ......................................................................... 34 Bank 2 Registers ......................................................................... 44 Bank 3 Registers ......................................................................... 47 Outline Dimensions ....................................................................... 62 Ordering Guide .......................................................................... 62
REVISION HISTORY
12/05--Preliminary Version D 7/05--Preliminary Version C 2/05--Preliminary Version B
1/05--Preliminary Version A
Rev. PrD | Page 2 of 64
Preliminary Technical Data SPECIFICATIONS
VCC = 2.7 V to 3.3 V, TA = -40oC to +85C, unless otherwise noted. Table 1.
Parameter CAPACITANCE-TO-DIGITAL CONVERTER Update Rate Resolution Range No Missing Codes Total Unadjusted Error Power Supply Rejection Output Noise (Peak-to-Peak) Parasitic Capacitance EXCITATION SOURCE Frequency Output Voltage Short-Circuit Current Maximum Output Load CSHIELD Output Drive CSHIELD Bias Level LOGIC INPUTS (SDI, SCLK, CS, SDA, GPI, TEST) VIH Input High Voltage VIL Input Low Voltage IIH Input High Voltage IIL Input Low Voltage Hysteresis OPEN-DRAIN OUTPUTS (SDO, SDA, INT) VOL Output Low Voltage IOH Output High Leakage Current LOGIC OUTPUTS VOL Output Low Voltage VOH Output High Voltage Floating State Leakage Current POWER AVCC, DVCC VDRIVE ICC Min 30 16 2 16 TBD 500 10 60 Typ Max Unit Hz Bit pF Bit fF aF/V aF/Hz pF
AD7142/AD7142-1
Test Conditions/Comments Maximum programmed sequence length
Guaranteed by design, but not production tested
Parasitic capacitance to ground, guaranteed by characterization
TBD
240 10 500 10 AVCC/2
TBD AVCC
kHz V mA pF A V V V A A mV V A V V A V V mA A A
Capacitance load on source to ground
0.7 x VDRIVE 0.3 x VDRIVE -1 1 150 0.4 1 0.4 VDRIVE - 0.6 10 2.7 1.65 1 50 2 3.6 DVCC + 0.3 TBD TBD TBD
0.1
ISINK = -1 mA VOUT = VDRIVE ISINK = 1 mA, VDRIVE = 1.6 V to DVCC + 0.3 V ISOURCE = 1 mA Pin tri-stated
Serial interface operating voltage Full power mode Low power mode (conversion delay = 400 ms) Full shutdown
Rev. PrD | Page 3 of 64
AD7142/AD7142-1
SPI TIMING SPECIFICATIONS AD7142
Preliminary Technical Data
TA = -40C to +105C; VDRIVE = 1.8 V to 3.6 V; AVCC, DVCC = 2.7 V to 3.6 V, unless otherwise noted. Sample tested at 25C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. Table 2. SPI Timing Specifications
Parameter fSCLK 1 t1 t2 t3 t4 t5 t6 t7 t8
1
Limit at TMIN, TMAX 10 10 5 20 20 15 15 20 16 TBD
Unit kHz min MHz max ns min ns min ns min ns min ns min ns max ns max ns
Description
CS falling edge to first SCLK falling edge SCLK high pulse width SCLK low pulse width SDI set-up time SDI hold time SDO access time after SCLK falling edge CS rising edge to SDO high impedance SCLK rising edge to CS high
Mark/space ratio (duty cycle) for the DCLK input is 40/60 to 60/40.
CS
t1
t2
1 2
t3
3 15 16 1 2 15
t8
16
SCLK
t4 t5
SDI MSB LSB
t6
SDO MSB LSB
t7
05702-002
Figure 2. SPI Detailed Timing Diagram
Rev. PrD | Page 4 of 64
Preliminary Technical Data
I2C TIMING SPECIFICATIONS AD7142-1
TA = -40C to +105C; VDRIVE = 1.8 V to 3.6 V; AVCC, DVCC = 2.7 V to 3.6 V, unless otherwise noted. Sample tested at 25C to ensure compliance. All input signals timed from a voltage level of 1.6 V. Table 3. I2C Timing Specifications 1
Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 tR tF
1
AD7142/AD7142-1
Limit 400 0.6 1.3 0.6 100 50 0.6 0.6 1.3 300 300
Unit kHz max s min s min s min ns min ns min s min s min s min ns max ns max
Description Start condition hold time, tHD; STA Clock low period, between 10% points, tLOW Clock high period, between 90% points, tHIGH Data setup time , tSU; DAT Data hold time, tHD; DAT Stop condition setup time, tSU; STO Start condition setup time, tSU; STA Bus free time between stop and start conditions, tBUF Clock/data rise time Clock/data fall time
Guaranteed by design, but not production tested.
t2
SCLK
tR
tF
t1
t1 t5
SDATA
t3 t4
t7
t6
STOP START
START
STOP
Figure 3. I2C Detailed Timing Diagram
Rev. PrD | Page 5 of 64
05702-003
t8
AD7142/AD7142-1 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter AVCC to AGND, DVCC to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Input Current to Any Pin Except Supplies1 ESD Rating Operating Temperature Range Storage Temperature Range Junction Temperature LFCSP Package Power Dissipation JA Thermal Impedance IR Reflow Peak Temperature Lead Temperature (Soldering 10 sec)
1
Preliminary Technical Data
Rating -0.3 V to +3.6 V -0.3 V to AVCC + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V 10 mA 2.5 kV -40C to +105C -65C to +150C 150C 450 mW 135.7C/W 260C (0.5C) 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
200A IOL
TO OUTPUT PIN
1.6V CL 50pF 200A IOH
05702-004
Figure 4. Load Circuit for Digital Output Timing Specifications
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrD | Page 6 of 64
Preliminary Technical Data PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
CIN2 CIN1 CIN0 VREF- VREF+ TEST GPIO INT 32 31 30 29 28 27 26 25
AD7142/AD7142-1
CIN2 CIN1 CIN0 VREF- VREF+ TEST GPIO INT
CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
AD7142
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
CS SCLK SDI SDO VDRIVE DGND2 DGND1 DVCC
32 31 30 29 28 27 26 25
CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
AD7142-1
TOP VIEW (Not to Scale)
24 23 22 21 20 19 18 17
ADD1 SCLK ADD0 SDA VDRIVE DGND2 DGND1 DVCC
CIN11 9 CIN12 10 CIN13 11 CSHIELD 12 AVCC 13 AGND 14 SRC 15 SRC 16
CIN11 9 CIN12 10 CIN13 11 CSHIELD 12 AVCC 13 AGND 14 SRC 15 SRC 16
Figure 5. AD7142, 32-Lead LFCSP Pin Configuration
05702-005
Figure 6. AD7142-1, 32-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN11 CIN12 CIN13 CSHIELD AVCC AGND SRC SRC DVCC DGND1 DGND2 VDRIVE SDO SDA SDI ADD0 SCLK CS ADD1 INT GPIO TEST VREF+ VREF- CIN0 CIN1 CIN2 Description Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input. CDC Shield Potential Output. Requires 10 nF capacitor to ground. Connect to external shield. CDC Supply Voltage. Analog Ground Reference Point for All CDC Circuitry. Tie to analog ground plane. CDC Excitation Source Output. Inverted Excitation Source Output. Digital Core Supply Voltage. Digital Ground. Digital Ground. Serial Interface Operating Voltage Supply. AD7142 SPI Serial Data Output. AD7142-1 I2C Serial Data Input/Output. SDA requires pull-up resistor. AD7142 SPI Serial Data Input. AD7142-1 I2C Address Bit 0. Clock Input for Serial Interface. AD7142 SPI Chip Select Signal. AD7142-1 I2C Address Bit 1. General Purpose Interrupt Output. Programmable polarity. Requires pull-up resistor. Programmable GPIO. Factory Test Pin. Tie to ground. CDC Positive Reference Input. Normally tied to analog power. CDC Negative Reference Input. Tie to analog ground. Capacitance Sensor Input. Capacitance Sensor Input. Capacitance Sensor Input.
Rev. PrD | Page 7 of 64
05702-044
AD7142/AD7142-1 TYPICAL PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
Figure 7. Supply Current vs. AVDD
Rev. PrD | Page 8 of 64
Preliminary Technical Data THEORY OF OPERATION
The AD7142 and AD7142-1 are capacitance-to-digital converters (CDCs) with on-chip environmental compensation, intended for use in portable systems requiring high resolution user input. The internal circuitry consists of a 16-bit, - converter that converts a capacitive input signal into a digital value. There are 14 input pins on the AD7142 and AD7142-1, CIN0 to CIN13. A switch matrix routes the input signals to the CDC. The result of each capacitance-to-digital conversion is stored in on-chip registers. The host subsequently reads the results over the serial interface. The AD7142 contains an SPI interface and the AD7142-1 has an I2C interface ensuring that the parts are compatible with a wide range of host processors. Because the AD7142 and AD7142-1 are identical parts, with the exception of the serial interface, AD7142 refers to both the AD7142 and AD7142-1 throughout this data sheet. The AD7142 interfaces with to up to 14 external capacitance sensors. These sensors can be arranged as buttons, scroll bars, joypads, or as a combination of sensor types. The external sensors consist of electrodes on a 2- or 4-layer PCB that interfaces directly to the AD7142. The AD7142 can be set up to implement any set of input sensors by programming the on-chip registers. The registers can also be programmed to control features such as averaging, offsets, and gains for each of the external sensors. There is a sequencer on-chip to control how each of the capacitance inputs is polled. The AD7142 has on-chip digital logic and 528 words of RAM that are used for environmental compensation. The effects of humidity, temperature, and other environmental factors can effect the operation of capacitance sensors. Transparent to the user, the AD7142 performs continuous calibration to compensate for these effects, allowing the AD7142 to give error-free results at all times. The AD7142 requires some minor companion software that runs on the host or other microcontroller to implement sensor functions such as a scroll bar or joypad. However, no companion software is required to implement buttons, including 8-way button functionality. The algorithms required for button sensors are implemented in digital logic on-chip. The AD7142 can be programmed to operate in either always powered mode, or in an automatic wake-up mode. The auto wake-up mode is particularly suited for portable devices that require low power operation giving the user significant power savings coupled with full functionality.
AD7142/AD7142-1
The AD7142 has a general interrupt output, INT, to indicate when new data has been placed into the registers. INT is used to interrupt the host on sensor activation. The AD7142 operates from a 2.7 V to 3.6 V supply, and is available in a 32-lead, 5 mm x 5 mm LFCSP.
CAPACITANCE SENSING THEORY
The AD7142 uses a method of sensing capacitance known as the shunt method. Using this method, an excitation source is connected to a transmitter generating an electric field to a receiver. The field lines measured at the receiver are translated into the digital domain by a - converter. When a finger, or other grounded object, interferes with the electric field, some of the field lines are shunted to ground and do not reach the receiver (see Figure 8). Therefore, the total capacitance measured at the receiver decreases when an object comes close to the induced field.
RX 16-BIT DATA
TX
Figure 8. Sensing Capacitance Method
In practice, the excitation source and - ADC are implemented on the AD7142, while the transmitter and receiver are constructed on a PCB that makes up the external sensor.
Registering a Sensor Activation
When a sensor is approached, the total capacitance associated with that sensor, measured by the AD7142, changes. When the capacitance changes to such an extent that a set threshold is exceeded, the AD7142 registers this as a sensor touch. For example, consider the case of two button sensors that are connected to the AD7142 in a differential manner. When one button is activated, the AD7142 registers an increase in capacitance; if the other button is activated, the AD7142 registers a decrease in capacitance. If neither of the buttons are activated, the AD7142 measures the background or ambient capacitance level.
Rev. PrD | Page 9 of 64
05702-007
- ADC
EXCITATION SIGNAL 240KHz
AD7142/AD7142-1
Preprogrammed threshold levels are used to determine if a change in capacitance is due to a button being activated. If the capacitance exceeds one of the threshold limits, the AD7142 registers this as a true button activation. The same thresholds principle is used to determine if other types of sensors, such as sliders or joypads, are activated.
Preliminary Technical Data
The power-on default setting of the POWER_MODE bits is 00, full power mode.
Full Power Mode
In full power mode, all sections of the AD7142 remain fully powered at all times. While a sensor is being touched, the AD7142 processes the sensor data. If no sensor is touched, the AD7142 measures the ambient capacitance level and uses this data for the on-chip compensation routines. In full power mode, the AD7142 converts at a constant rate. See the CDC Conversion Time section for more information.
Complete Solution for Capacitance Sensing
Analog Devices provides a complete solution for capacitance sensing. The two main elements to the solution are the sensor PCB and the AD7142. If the application requires sensors in the shape of a slider or joypad, software is required that runs on the host processor. (No software is required for button sensors.) The software typically requires 3 kB of code and 500 bytes of data memory for a slider sensor.
SENSOR PCB
Low Power Mode
When in low power mode, the AD7142 POWER_MODE bits are set to 10 upon device initialization. If the external sensors are not touched, the AD7142 reduces its conversion frequency, thereby greatly reducing its power consumption. The part remains in a low power state while the sensors are not touched. Every 400 ms, the AD7142 performs a conversion and uses this data to update the compensation logic. When an external sensor is touched, the AD7142 begins a conversion sequence every 40 ms to read back data from the sensors. In low power mode, the total current consumption of the AD7142 is an average of the current used during a conversion, and the current used while the AD7142 is waiting for the next conversion to begin. For example, when the low power mode conversion interval is 400 ms, the AD7142 uses typically 0.9 mA current for 40 ms, and 15 A for 360 ms of the conversion interval. (Note that these conversion timings can be altered through the register settings. See the CDC Conversion Time section for more information.)
AD7142 SETUP AND INITIALIZATION POWER_MODE = 10
SPI or I2C AD7142
Figure 9. 3-Part Capacitance Sensing Solution
Analog Devices supplies the sensor PCB design to the customer based on the customer's specifications, and supplies any necessary software on an open-source basis. Standard sensor designs are also available as PCB library components.
OPERATING MODES
The AD7142 has three operating modes. Full power mode, where the device is always fully powered, is suited for applications where power is not a concern, for example game consoles that have an ac power supply. Low power mode, where the part automatically powers down, is tailored to give significant power savings over full power mode, and is suited for mobile applications where power must be conserved. The AD7142 also has a complete shutdown mode. The POWER_MODE bits (Bit 0 and Bit 1) of the control register set the operating mode on the AD7142. The control register is at Address 0x000.
05702-008
HOST PROCESSOR 1 MIPS 3kB ROM 500BYTES RAM
NO
ANY SENSOR TOUCHED? YES
CONVERSIONS EVERY 400ms UPDATE COMPENSATION LOGIC DATA PATH
SEQUENCER-CONTROLLED CONVERSIONS ON ALL SENSORS EVERY 40ms
NO
Table 6. POWER_MODE Settings
POWER_MODE Bits 00 01 10 11 Operating Mode Full power mode Full shutdown mode Low power mode Full shutdown mode
ANY SENSOR TOUCHED?
YES YES ANY SENSOR TOUCHED?
NO
Table 6 shows the POWER_MODE settings for each operating mode. To put the AD7142 into shutdown mode, set the POWER_MODE bits to either 01 or 11.
Figure 10. Low Power Mode Operation
Rev. PrD | Page 10 of 64
05702-009
TIMEOUT
PROXIMITY TIMER COUNT DOWN
Preliminary Technical Data CAPACITANCE SENSOR INPUT CONFIGURATION
Each stage of the AD7142 capacitance sensors can be uniquely configured by using the registers in Table 53 and Table 54. These registers are used to configure input pin connection set ups, sensor offsets, sensor sensitivities, and sensor limits for each stage. Apply this feature to optimize the function of each sensor to the application. For example, a button sensor connected to STAGE0 may require a different sensitivity and offset values than a button with a different function that is connected to a different stage.
AD7142/AD7142-1
The AD7142 has an on-chip multiplexer to route the input signals from each pin to the input of the converter. Each input pin can be tied to either the negative or the positive input of the CDC, or it can be left floating. Each input can also be internally connected to the CSHIELD signal to help prevent cross coupling. If an input is not used, always connect it to CSHIELD. For each input pin, CIN0 to CIN13, the multiplexer settings can be set on a per sequencer stage basis. For example, CIN0 is connected to the negative CDC input for conversion STAGE1, left floating for sequencer STAGE1, and so on for all twelve conversion stages. Two bits in each register control the mux setting for the input pin.
CIN INPUT MULTIPLEXER SETUP
The CIN_CONNECTION_SETUP registers in Table 53 list the different options that are provided for connecting the sensor input pin to the CDC converter.
CIN0 CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN11 CIN12 CIN13
CIN_CONNECTION _SETUP BITS 00 01 10 11
CIN SETTING CINX FLOATING CINX CONNECTED TO NEGATIVE CDC INPUT CINX CONNECTED TO POSITIVE CDC INPUT CINX CONNECTED TO CSHIELD + CDC -
05702-010
Figure 11. Input Mux Configuration Options
Rev. PrD | Page 11 of 64
AD7142/AD7142-1 CAPACITIANCE-TO-DIGITAL CONVERTER
The capacitance-to-digital converter on the AD7142 has a sigma-delta (-) architecture with 16-bit resolution. There are 14 possible inputs to the CDC that are connected to the input of the converter through a switch matrix. The sampling frequency of the CDC is 240 kHz.
Preliminary Technical Data
+DAC (20pF RANGE)
7
POS_AFE_OFFSET REGISTER
POS_AFE_OFFSET_SWAP REGISTER CIN + 16-BIT _ CDC 16
OVERSAMPLING THE CDC OUTPUT
It is possible to sample the result of any CDC conversion at a rate less than 240 kHz. The decimation rate, or over-sampling ratio, is determined by Bits[9:8] of the control register, as listed in Table 7. Table 7. CDC Decimation Rate
Decimation Bit Value 00 01 10 11 Decimation Rate 256 128 64 64 CDC Sample Rate 312.5 Hz 625 Hz 1.25 kHz 1.25 kHz
SENSOR
NEG_AFE_OFFSET_SWAP REGISTER
EXT
-DAC (20pF RANGE)
7
NEG_AFE_OFFSET REGISTER
05702-011
CIN_CONNECTION_SETUP REGISTER
Figure 12. Analog Front End Offset Control
The decimation process on the AD7142 is an averaging process where a number of samples are taken and the averaged result is output. The amount of samples taken is set equal to the decimation rate, so 256, 128, or 64 samples are averaged to obtain the CDC output. The decimation process reduces the amount of noise present in the final CDC result. However, the higher the decimation rate, the lower the sampling frequency, thus, a tradeoff is required between a noise-free signal and speed of sampling.
CONVERSION SEQUENCER
The AD7142 has an on-chip sequencer to implement conversion control for the input channels. Up to 12 conversion stages can be performed in sequence. By using the Bank 2 registers, each stage can be uniquely configured to support multiple capacitance sensor interface requirements. For example, a slider sensor can be assigned to STAGE1 with a button sensor assigned to STAGE2. The AD7142 on-chip sequencer controller provides conversion control beginning with STAGE0. Figure 13 shows a block diagram of the CDC conversion stages and CIN inputs. A conversion sequence is defined as a sequence of CDC conversion starting at STAGE0 and ending at the stage determined by the value programmed in the SEQUENCE_STAGE_NUM register. In Figure 14, the conversion sequence is from STAGE0 through STAGE5. Depending on the number and type of capacitance sensors that are used, not all conversion stages are required. Use the SEQUENCE_STAGE_NUM register to set the number of conversions in one sequence, depending on the sensor interface requirements. For example, this register would be set to 5 if the CIN inputs were mapped to only six stages as shown in Figure 14. In addition, set the STAGE_CAL_EN registers according to the number of stages that are used.
CAPACITANCE SENSOR OFFSET CONTROL
Apply the STAGE_OFFSET registers to null any capacitance sensor offsets associated with printed circuit board parasitic capacitance, or capacitance due to any other source, such as connectors. This is only required once during the initial capacitance sensor characterization. A simplified block diagram in Figure 12 shows how to apply the STAGE_OFFSET registers to null the offsets. The 7-bit POS_AFE_OFFSET and NEG_AFE_OFFSET registers provide 0.16 pF resolution offset adjustment over a range of 20 pF. Apply the positive and negative offsets to either the positive or the negative CDC input using the NEG_AFE_OFFSET and POS_AFE_OFFSET registers.
Rev. PrD | Page 12 of 64
Preliminary Technical Data
STAGE 11 STAGE 10 STAGE 9 STAGE 8 STAGE 7 STAGE 6 STAGE 5 STAGE 4 STAGE 3 STAGE 2 STAGE 1 STAGE 0 CIN0 CIN1 CIN2
SWITCH MATRIX
AD7142/AD7142-1
AD7142 SEQUENCER
STAGE 0 + - CDC
BUTTONS
CIN1 CIN2
STAGE 1 + CDC -
STAGE 2 SLIDER + - CDC
CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN1 1 CIN12 CIN13
SE QU EN CE
- 16-BIT ADC
CIN3 CIN4
STAGE 3 + CDC -
CO NV ER SIO N
8-WAY SWITCH CIN5 CIN6 STAGE 4 + CDC -
05702-012
Figure 13. AD7142 CDC Conversion Stages
CIN7 CIN8
STAGE 5 + - CDC
05702-014
STAGE 11 STAGE 10 STAGE 9 STAGE 8 STAGE 7 STAGE 6 STAGE 5 STAGE 4 STAGE 3 STAGE 2 STAGE 1 STAGE 0 CIN0 CIN1 CIN2
SWITCH MATRIX
Figure 15. Sequencer Setup for Sensors
A button sensor generally requires one sequencer stage; however, it is possible to configure two button sensors to operate differentially. Only one button from the pair can be activated at a time; pressing both buttons together results in neither button being activated. This configuration requires one conversion stage. A slider sensor requires two stages: one stage for sensor activation; the other stage for measuring positional data from the slider. In Figure 15, the slider activation uses STAGE2, while the positional data uses STAGE3. The 8-way switch is made from two pairs of differential buttons. It, therefore, requires two conversion stages, one for each of the differential button pairs. The buttons are orientated so that one pair makes up the top and bottom portions of the 8-way switch; the other pair makes up the left and right portions of the 8-way switch.
CIN3 CIN4 CIN5 CIN6 CIN7 CIN8 CIN9 CIN10 CIN1 1 CIN12 CIN13
- 16-BIT ADC
FF_SKIP_CNT
SEQUENCE_CONV_NUM
05702-013
NOTES 1. SEQUENCE_STAGE_NUM = 5. 2. FF_SKIP_CNT = 3 (VALUE SELECTED FROM TABLE 8 FOR DECIMATION = 128).
CDC CONVERSION TIME
The time required for one complete measurement by the CDC is defined as the CDC conversion time. For optimal system performance, configure the AD7142 CDC conversion time within a range of 35 ms to 40 ms. The SEQUENCE_STAGE_NUM, FF_SKIP_CNT, and DECIMATION registers determine the conversion time as listed in Table 8.
Figure 14. Example Using SEQUENCE_CON_NUM and FF_SKIP_CNT Registers
The number of required conversion stages depends wholly on the number of sensors attached to the AD7142. Figure 15 shows how many conversion stages are required for each sensor, and how many inputs to the AD7142 each sensor requires.
Rev. PrD | Page 13 of 64
AD7142/AD7142-1
Table 8. CDC Conversion Times for Full Power Mode
DECIMATION = 64 CDC Conversion Time (ms) FF_SKIP_CNT 11 9.2 11 18.4 11 27.6 11 36.8 9 38.4 7 36.8 6 37.6 5 36.8 4 34.5 4 38.4 3 33.8 3 36.8
Preliminary Technical Data
DECIMATION = 128 CDC Conversion FF_SKIP_CNT Time (ms) 11 18.4 11 36.8 7 36.8 5 36.8 4 38.4 3 36.8 2 32.2 2 36.8 2 41.4 1 30.7 1 33.8 1 36.8 DECIMATION = 256 CDC Conversion FF_SKIP_CNT Time (ms) 11 36.5 5 36.5 3 36.5 2 36.5 2 46.0 1 36.8 1 43.0 1 49.1 0 27.6 0 30.7 0 33.7 0 36.8
SEQUENCE_STAGE_NUM 0 1 2 3 4 5 6 7 8 9 10 11
For example, while operating with a decimation rate of 128, if the SEQUENCE_STAGE_NUM register is set to 5 for the conversion of six stages in a sequence, the FF_SKIP_CNT register should be set to 3 resulting in a conversion time of 36.8 ms. This example is shown in Figure 14. Determining the FF_SKIP_CNT value is only required one time during the initial setup of the capacitance sensor interface. This value determines which CDC samples are not used (skipped) in the proximity detection fast FIFO.
LP_CONV_DELAY is set to 3. With a setting of 3, the AD7142 automatically wakes up, performing a conversion every 400 ms. Table 9. LP_CONV_DELAY Settings
LP_CONV_DELAY BITS 00 01 10 11 Delay Between Conversions 100 ms 200 ms 300 ms 400 ms
Full Power Mode CDC Conversion Time
The full power mode CDC conversion time is set by configuring the SEQUENCE_STAGE_NUM, FF_SKIP_CNT and DECIMATION registers as outlined in Table 8. Figure 16 shows a simplified timing diagram of the full power CDC conversion time. The full power mode CDC conversion time tCONV_FP is set using Table 8.
tCONV_FP
CDC CONVERSION CONVERSION N CONVERSION N+1 CONVERSION N+2
05702-015
Figure 17 shows a simplified timing example of the low power CDC conversion time. As shown, the low power CDC conversion time is set by tCONV_FP and the LP_CONV_DELAY register.
tCONV_LP
CDC CONVERSION
CONVERSION N
CONVERSION N + 1
05702-016
NOTES 1. tCONV_LP = tCONV_FP + LP_CONV_DELAY
Figure 17. Low Power Mode CDC Conversion Time CDC Conversion Results
CDC CONVERSION RESULTS
Certain applications, such as a slider function, require reading back the CDC conversion results for host processing. The registers required for host processing are located in Register Bank 3. The host processes the data read back from these registers to determine relative position information. In addition to the results registers in Bank 3, the AD7142 provides the 16-bit CDC output data directly starting at Address 0x00B of Register Bank 1. Reading back the CDC 16-bit conversion data register allows for customer specific application data processing.
NOTES 1. tCONV_FP = VALUE SET FROM TABLE 8.
Figure 16. Full Power Mode CDC Conversion Time
Low Power Mode CDC Conversion Time with Delay
The frequency of each CDC conversion while operating in the low power automatic wake up mode is controlled by using the LP_CONV_DELAY register bits (Bits[3:2] in Register 0x00), in addition to the registers listed in Table 8. This feature provides some flexibility for optimizing the conversion time to meet system requirements vs. AD7142 power consumption. For example, maximum power savings is achieved when the
Rev. PrD | Page 14 of 64
Preliminary Technical Data NON-CONTACT PROXIMITY DETECTION
The AD7142 internal signal processing continuously monitors all capacitance sensors for non-contact proximity detection. This feature provides the ability to detect when a user is approaching a sensor, at which time all internal calibration is immediately disabled while the AD7142 is automatically configured to detect a valid contact. The proximity control register bits are described in Table 10. The FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register bits control how long the calibration disable period is after proximity is detected. The calibration is disabled during this time and enabled again at the end of this period provided that the user is no longer approaching, or in contact with, the sensor. Figure 18 and Figure 19 show examples of how these registers are used to set the full and low power mode calibration disable periods.
AD7142/AD7142-1
register bits to force a recalibration while operating in the full and low power modes. These figures show a user approaching a sensor followed by the user leaving the sensor while the proximity detection remained active after the user left the sensor. This situation could occur if the user interaction created some moisture on the sensor for example thus causing the new sensor value to be different from the expected value. In this case, the internal recalibration would be applied to automatically recalibrate the sensor. The force calibration event takes two interrupt cycles: nothing should be read from or written to the AD7142 during the recalibration period.
Proximity Sensitivity
There are two conditions that set the internal proximity detection signal as described in Figure 22 with Comparator 1 and Comparator 2. Comparator 1 detects when a user is approaching a sensor. The sensitivity of Comparator 1 is controlled by PROXIMITY_DETECTION_RATE. For example, if PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1 signal is set when the absolute difference between WORD1 and WORD3 exceed four LSB codes. Comparator 2 detects when a user is hovering over a sensor or approaches a sensor very slowly. The sensitivity of Comparator 2 is controlled by the PROXIMITY_RECAL_LVL in Register 0x003. For example, if PROXIMITY_RECAL_LVL is set to 75, the Proximity 2 signal is set when the absolute difference between the fast filter average value and the ambient value exceeds 75 LSB codes.
Recalibration
In the event of a very long proximity detection event, such as a user hovering over a sensor for a long period of time, the FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL bits in register 0x004 can be applied to force a recalibration. This feature ensures that the ambient values are recalibrated regardless of how long the user may be hovering over a sensor. A recalibration ensures maximum AD7142 sensor performance. Figure 20 and Figure 21 show examples of using the FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL
Table 10. Proximity Control Registers (Refer to Figure 22)
Register FP_PROXIMITY_CNT LP_PROXIMITY_CNT FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL PROXIMITY_RECAL_LVL PROXIMITY_DETECTION_RATE Length (Bits) 4 4 8 6 8 6 Register Address 0x002 0x002 0x004 0x004 0x003 0x003 Description Full power mode proximity control Low power mode proximity control Full power mode proximity recalibration control Low power mode proximity recalibration control Proximity recalibration level Proximity detection rate
USER APPROCHES SENSOR HERE
USER LEAVES SENSOR AREA HERE
tCONV_FP
CDC CONVERSIONS (INTERNAL)
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 tCALDIS
PROXIMITY DETECTION (INTERNAL)
CALIBRATION (INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
Figure 18. Full Power Mode Proximity Detection Example with FP_PROXIMITY = 1
Rev. PrD | Page 15 of 64
05702-017
AD7142/AD7142-1
USER APPROCHES SENSOR HERE USER LEAVES SENSOR AREA HERE
Preliminary Technical Data
tCONV_FP
CDC CONVERSIONS (INTERNAL)
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 tCALDIS
PROXIMITY DETECTION (INTERNAL)
CALIBRATION (INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
Figure 19. Low Power Mode Proximity Detection with LP_PROXIMITY = 4 and LP_CONV_DELAY = 0
USER APPROCHES SENSOR HERE
USER LEAVES SENSOR AREA HERE
USER IN CONTACT WITH SENSOR
CDC CONVERSION VALUES EXCEED PROXIMITY_RECALIBRATION _LVL
16
CDC CONVERSIONS (INTERNAL)
30
70
tDISCAL
PROXIMITY DETECTION (INTERNAL)
CALIBRATION (INTERNAL)
CALIBRATION DISABLED
RECALIBRATION PERIOD
CALIBRATION ENABLED
NOTES 1. CONVERSION TIME tCONV_FP DETERMINED FROM TABLE 8 2. tDISCAL = tCONV_FP x FP_PROXIMITY_CNT) 3. tRECAL = (tCONV_FP x FP_PROXIMITY_RECAL)
Figure 20. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMITY = 1 and FP_PROXIMITY_RECAL = 40
Rev. PrD | Page 16 of 64
05702-019
RECALIBRATION (INTERNAL)
tRECAL
05702-018
NOTES 1. CONVERSION TIME tCONV_LP = (tCONV_FP + LP_CONV_DELAY). 2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED. 3. tCALDIS = (tCONV_LP x LP_PROXIMITY_CNT x 4) + LP_CONV_DELAY.
tCONV_FP
Preliminary Technical Data
USER APPROCHES SENSOR HERE USER LEAVES SENSOR AREA HERE
AD7142/AD7142-1
USER IN CONTACT WITH SENSOR
CDC CONVERSION VALUES EXCEED PROXIMITY_RECALIBRATION _LVL
16
CDC CONVERSIONS (INTERNAL)
30
70
tCONV_FP
tDISCAL
PROXIMITY DETECTION (INTERNAL)
CALIBRATION (INTERNAL)
CALIBRATION DISABLED
RECALIBRATION PERIOD
CALIBRATION ENABLED
RECALIBRATION (INTERNAL)
tRECAL
Figure 21. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMITY = 4 and LP_PROXIMITY_RECAL = 10
Rev. PrD | Page 17 of 64
05702-020
NOTES 1. CONVERSION TIME tCONV_LP = tCONV_HP + LP_CONV_DELAY. 2. tDISCAL = tCONV_LP x (16 x LP_PROXIMITY_CNT) 3. tRECAL = (tCONV_LP x LP_PROXIMITY_RECAL x 4)
AD7142/AD7142-1
Preliminary Technical Data
STAGE_MAX_WORD0 STAGE_MAX_WORD1 STAGE_MAX_WORD2 STAGE_MAX_WORD3 - 16-BIT CDC 16 BANK 3 REGISTERS
MAX LEVEL DETECTION LOGIC
STAGE_MAX_AVG BANK 3 REGISTERS STAGE_MAX_TEMP BANK 3 REGISTERS STAGE_HIGH_THRESHOLD BANK 3 REGISTERS STAGE_MIN_WORD0 STAGE_MIN_WORD1 STAGE_MIN_WORD2 STAGE_MIN_WORD3 BANK 3 REGISTERS
MIN LEVEL DETECTION LOGIC
CONTROL LOGIC SW SLOW_FILTER_UPDATE_LVL REGISTER 0x003
STAGE_MIN_AVG BANK 3 REGISTER3 STAGE_MIN_TEMP BANK 3 REGISTERS STAGE_LOW_THRESHOLD BANK 3 REGISTERS FP_PROXIMITY_CNT REGISTER 0x004 LP_PROXIMITY_CNT REGISTER 0X004
COMPARATOR 3 WORD 0 - WORD 3
STAGE_FF_WORD0 STAGE_FF_WORD1 STAGE_FF_WORD2 STAGE_FF_WORD3 STAGE_FF_WORD4 STAGE_FF_WORD5 STAGE_FF_WORD6 STAGE_FF_WORD7
COMPARATOR 1 PROXIMITY 1 WORD 0 - WORD 3 PROXIMITY PROXIMITY TIMING CONTROL LOGIC
PROXIMITY
SLOW FILTER EN
PROXIMITY_DETECTION_RATE REGISTER 0x003
FP_PROXIMITY_RECAL REGISTER 0x004
LP_PROXIMITY_RECAL REGISTER 0X004
=WORD(N) N0
8 SW1 COMPARATOR 2 AVERAGE - AMBIENT STAGE_SF_WORD0 STAGE_SF_WORD1 STAGE_SF_WORD2 STAGE_SF_WORD3 STAGE_SF_WORD4 STAGE_SF_WORD5 STAGE_SF_WORD6 STAGE_SF_WORD7 BANK 3 REGISTERS STAGE_SF_AMBIENT BANK 3 REGISTERS PROXIMITY_RECAL_LVL REGISTER 0x003 STAGE_FF_AVG BANK 3 REGISTERS
7
PROXIMITY 2
BANK 3 REGISTERS
STAGE_FF_WORDX
CDC OUTPUT CODE
AMBIENT VALUE STAGE_SF_WORDX SENSOR CONTACT TIME
NOTES 1. SLOW FILTER EN IS SET AND SW1 IS CLOSED WHEN /WORD 0-WORD 3/ EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE REGISTER PROVIDING PROXIMITY IS NOT SET. 2. PROXIMITY 1 IS SET WHEN /WORD 0-WORD 3/ EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE REGISTER. 3. PROXIMITY 2 IS SET WHEN /AVERAGE-AMBIENT/ EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER. 4. DESCRIPTION OF COMPARATOR FUNCTIONS: COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR. COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR, OR APPROACHING A SENSOR VERY SLOWLY. ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION. FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR. COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND PROXIMITY IS NOT SET.
Figure 22. AD7142 Proximity Detection and Environmental Calibration
Rev. PrD | Page 18 of 64
05702-021
Preliminary Technical Data ENVIRONMENTAL CALIBRATION
The AD7142 provides on-chip capacitance sensor calibration to automatically adjust for environmental conditions that have an effect on the capacitance sensor ambient levels. Capacitance sensor output levels are sensitive to temperature, humidity, and in some cases, dirt. The AD7142 achieves optimal and reliable sensor performance by continuously monitoring the CDC ambient levels and correcting for any changes by adjusting the initial STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW register values. The CDC ambient level is defined as the capacitance sensor output level during periods when the user is not approaching or in contact with the sensor. The compensation logic runs automatically on every conversion after configuration when the AD7142 is not being touched. This allows the AD7142 to account for rapidly changing environmental conditions. The ambient compensation control registers give the host access to general setup and controls for the compensation algorithm. The RAM stores the compensation data for each conversion stage, as well as setup information specific to each stage. Figure 23 shows an example of an ideal capacitance sensor behavior where the CDC ambient level remains constant regardless of the environmental conditions. In this example, the initial settings programmed in the STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW registers are sufficient to detect a sensor contact resulting with the AD7142 asserting the INT output when the offset levels are exceeded.
SENSOR 1 INT ASSERTED STAGE_OFFSET_HIGH (INITIAL REGISTER VALUE)
AD7142/AD7142-1
calibration algorithm prevents errors such as this from occurring.
SENSOR 1 INT ASSERTED STAGE_OFFSET_HIGH (INITIAL REGISTER VALUE)
CDC OUTPUT CODES
CDC AMBIENT VALUE DRIFTING
STAGE_OFFSET_LOW (INITIAL REGISTER VALUE) SENSOR 2 INT NOT ASSERTED t CHANGING ENVIRONMENTALCONDITIONS
05702-023
Figure 24. Typical Sensor Behavior without Calibration Applied
Capacitance Sensor Behavior with Calibration
The AD7142 on-chip adaptive calibration algorithm prevents sensor detection errors such the one shown in Figure 24. This is achieved by monitoring the CDC ambient levels and internally adjusting the initial offset level register values according to the amount of ambient drift measured on each sensor. This closed loop routine ensures the reliability and repeatability operation of every sensor connected to the AD7142 under dynamic environmental conditions. Figure 25 shows a simplified example of how the AD7142 applies the adaptive calibration process resulting in no interrupt errors under changing CDC ambient levels due to environmental conditions.
SENSOR 1 INT ASSERTED 2 1 CDC OUTPUT CODES 3 STAGE_OFFSET_HIGH (POST CALIBRATED REGISTER VALUE)
CDC OUTPUT CODES
CDC AMBIENT VALUE
CDC AMBIENT VALUE DRIFTING 6 5 4 SENSOR 2 INT ASSERTED t CHANGING ENVIRONMENTALCONDITIONS STAGE_OFFSET_LOW (POST CALIBRATED REGISTER VALUE)
STAGE_OFFSET_LOW (INITIAL REGISTER VALUE) SENSOR 2 INT ASSERTED t CHANGING ENVIRONMENTALCONDITIONS
05702-022
Figure 23. Ideal Sensor Behavior with a Constant Ambient Level
Capacitance Sensor Behavior Without Calibration
Figure 24 shows the typical behavior of a capacitance sensor with no applied calibration. This figure shows ambient levels drifting over time as environmental conditions change. The ambient level drift has resulted in the detection of a missed user contact on Sensor 2. This is a result of the initial low offset level remaining constant while the ambient levels drifted upward beyond the detection range. The Capacitance Sensor Behavior with Calibration section describes how the AD7142 adaptive
NOTES 1. INITIAL STAGE_OFFSET_HIGH REGISTER VALUE 2. POST CALIBRATED REGISTER STAGE_OFFSET_HIGH VALUE 3. POST CALIBRATED REGISTER STAGE_OFFSET_HIGH VALUE 4. INITIAL STAGE_OFFSET_LOW REGISTER VALUE 5. POST CALIBRATED REGISTER STAGE_OFFSET_LOW VALUE 6. POST CALIBRATED REGISTER STAGE_OFFSET_LOW VALUE
Figure 25. Typical Sensor Behavior with Calibration Applied on the Data Path
Rev. PrD | Page 19 of 64
05702-024
AD7142/AD7142-1 ADAPTIVE THRESHOLD AND SENSITIVITY
The AD7142 provides an on-chip self-learning adaptive threshold and sensitivity algorithm. This algorithm continuously monitors the output levels of each sensor and automatically rescales the threshold levels proportionally to the sensor area covered by the user. As a result, the AD7142 maintains optimal threshold and sensitivity levels for all types of users regardless of their finger sizes. The threshold level is always referenced from the ambient level and is defined as the CDC converter output level that must be exceeded for a valid sensor contact. The sensitivity level is defined as how sensitive the sensor is before a valid contact is registered. Figure 26 provides an example of how the adaptive threshold and sensitivity algorithm works. In a case where the adaptive threshold and sensitivity algorithm are disabled, the positive and negative sensor threshold levels are set by the
Preliminary Technical Data
STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW initial values. Reference A in Figure 26 shows that this results in an under sensitive threshold level for a small finger user, demonstrating the disadvantages of a fixed threshold level. By enabling the adaptive threshold and sensitivity algorithm, the positive and negative threshold levels are determined by the POS_THRESHOLD_SENSI TIVITY and NEG_THRESHOLD_SENSITIVITY register values and the most recent average maximum sensor output value. These registers can be used to select 16 different positive and negative sensitivity levels ranging between 25% and 95.32% of the most recent average maximum output level referenced from the ambient value. Reference B shows that the positive adaptive threshold level is set at almost mid sensitivity with a 62.51% threshold level by setting POS_THRESHOLD_SENSITIVITY = 1000. Figure 26 also provides a similar example for the negative threshold level with NEG_THRESHOLD_SENSITIVITY = 0001.
CDC OUTPUT CODES
AVERAGE MAX VALUE
95.32%
AVERAGE MAX VALUE A 95.32%
62.51% = POS ADAPTIVE THRESHOLD LEVEL
STAGE_OFFSET_HIGH (INITIAL VALUE) 25%
62.51% = POS ADAPTIVE THRESHOLD LEVEL B AMBIENT LEVEL 25% NEG ADAPTIVE THRESHOLD LEVEL = 39.08% 25% NEG ADAPTIVE THRESHOLD LEVEL = 39.08% 95.32%
25%
STAGE_OFFSET_LOW (INITIAL VALUE)
95.32% SENSOR CONTACTED BY SMALL FINGER SENSOR CONTACTED BY LARGE FINGER
05702-025
Figure 26. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011
Rev. PrD | Page 20 of 64
Preliminary Technical Data INTERRUPT OUTPUT
The AD7142 has an interrupt output that triggers an interrupt service routine on the host processor. The INT signal is on Pin 25, and is an open-drain output. There are three types of interrupt events on the AD7142: a CDC conversion complete interrupt, a sensor threshold interrupt, and a GPIO interrupt. Each interrupt has enable and status registers. The conversion complete and sensor threshold interrupts can be enabled on a per conversion stage basis. The status registers indicate what type of interrupt triggered the INT pin. Status registers are cleared, and the INT signal is reset high, during a read operation. The signal returns high as soon as the read address has been set up.
AD7142/AD7142-1
Register 0x00A is the conversion completion status register. Each bit in this register corresponds to a conversion stage. If a bit is set, it means that the conversion complete interrupt for the corresponding stage was triggered. This register is cleared on a read, provided the underlying condition that triggered the interrupt has gone away. (For a detailed register description, see Table 24.)
SENSOR THRESHOLD INTERRUPT
The AD7142 interrupt signal asserts low to indicate that a conversion result exceeds either the high or low threshold limits for that sensor. When a conversion result from a sensor exceeds the threshold limits, it indicates the sensor has been touched. The sensor threshold interrupt can be enabled independently for each conversion stage via the interrupt configuration registers. Register 0x05 is the low threshold interrupt enable register. Each bit in the register corresponds to the threshold low interrupt for conversion STAGE0 to STAGE11. Register 0x006 is the high threshold enable register. Each bit in this register, corresponds to the high threshold interrupt enable for conversion STAGE0 to STAGE11. Setting a bit to 1 enables the interrupt for that stage. Clearing a bit to 0 disables the interrupt for that stage. When a conversion result exceeds a low threshold, the status bit corresponding to that conversion stage is set in the CDC low limit status register at Address 0x008. (For a detailed register description, see Table 22.) If a conversion stage result exceeds a high limit, the status bit corresponding to that stage is set in the CDC high limit status register at Address 0x009. (For a detailed register description, see Table 23.) All bits in the status registers are cleared on read back, if all conversion results are within the threshold limits.
CDC CONVERSION COMPLETE INTERRUPT
The AD7142 interrupt signal asserts low to indicate the completion of a conversion stage, and new conversion result data is available in the registers. The interrupt can be independently enabled for each conversion stage. Each conversion stage complete interrupt can be enabled via the CDC Conversion Completion register (Address 0x007). This register has a bit that corresponds to each conversion stage. Setting this bit to 1 enables the interrupt for that stage. Clearing this bit to 0 disables the conversion complete interrupt for that stage. In normal operation, the AD7142 is set up to interrupt enable the last stage only in a conversion sequence. For example, if there are five conversion stages, the conversion complete interrupt for STAGE4 is enabled. INT only asserts when all five conversion stages are complete, and the host can read new data from all five result registers. The interrupt is cleared by reading the status register.
tCONV_FP
CONVERSIONS STAGE 0 STAGE 1 STAGE 2 STAGE 3 STAGE 4 STAGE 5
STAGE 6
STAGE 7
STAGE 8
STAGE 9
STAGE 1 0 STAGE 11
INT
1
3
5
2 SERIAL READS
4
6
STAGEx_SENSOR_HIGH_INT = STAGEx_SENSOR_LOW_INT = STAGEx_CONVERSION_I T = 0 FOR ALL STAGES HIGHLIGHTED IN GRAY N
Figure 27. Example of Configuring the Registers for End of Conversion Interrupt Set Up
Rev. PrD | Page 21 of 64
05702-026
PROGRAMMINGE NOTES 1. STAGE0_SENSOR_HIGH_INT = STAGE0_SENSOR_LOW_INT = 0, STAGE0_CONVERSION_INT = 1 2. READ-BACK FROM STAGE0_CONVERSION REGISTER TO RESET INT OUTPUT 3. STAGE5_SENSOR_HIGH_INT = STAGE5_SENSOR_LOW_INT = 0, STAGE5_CONVERSION_INT = 1 4. READ-BACK FROM STAGE5_CONVERSION REGISTER TO RESET INT OUTPUT 5. STAGE9_SENSOR_HIGH_INT = STAGE9_SENSOR_LOW_INT = 0, STAGE9_CONVERSION_INT = 1 6. READ-BACK FROM STAGE9_CONVERSION REGISTER TO RESET INT OUTPUT
AD7142/AD7142-1
tCONV_FP
CONVERSIONS STAGE 0 STAGE 1 STAGE 2 STAGE 3 STAGE 4 STAGE 5 STAGE 6 STAGE 7
Preliminary Technical Data
STAGE 8
STAGE 9
STAGE 10
STAGE 11
INT
1
3
2 SERIAL READS
4
4
NOTES THIS EXAMPLE ASSUMES THAT SENSOR CONTACT FOR STAGE0 EXCEEDED THE HIGH THRESHOLD LIMIT THIS EXAMPLE ASSUMES THAT SENSOR CONTACT FOR STAGE9 EXCEEDED THE LOW THRESHOLD LIMIT PROGRAMMING NOTES 1. STAGE0_SENSOR_HIGH_INT = 1, STAGE0_SENSOR_LOW_INT = STAGE0_CONVERSION_INT = 0 2. READ-BACK FROM STAGE0_HIGH_LIMIT REGISTER TO RESET INT OUTPUT 3. STAGE9_SENSOR_HIGH_INT = 0, STAGE5_SENSOR_LOW_INT = 1, STAGE5_CONVERSION_INT = 0 4. READ-BACK FROM STAGE0_LOW_LIMIT REGISTER TO RESET INT OUTPUT STAGEx_SENSOR_HIGH_INT = STAGEx_SENSOR_LOW_INT = STAGEx_CONVERSION_INT = 0 FOR ALL STAGES HIGHLIGHTED IN GRAY
Figure 28. Example of Configuring the Registers for Sensor Interrupt Set Up
Table 11. GPIO Interrupt Behavior
GPIO_INPUT_CONFIG 00 = negative level triggered 00 = negative level triggered 01 = positive edge triggered 01 = positive edge triggered 10 = negative edge triggered 10 = negative edge triggered 11 = positive level triggered 11 = positive level triggered GPIO Pin 1 0 1 0 1 0 1 0 GPIO_STATUS 0 1 1 0 0 1 1 0 INT 1 0 0 1 1 0 0 1 INT Behavior Not triggered Asserted while signal on GPIO pin is low Pulses low at low to high GPIO transition Not triggered Pulses low at high to low GPIO transition Not triggered Asserted while signal on GPIO pin is high Not triggered
GPIO INT OUTPUT CONTROL
The INT output signal can be controlled by the GPIO pin when the GPIO is configured as an input. The GPIO is configured as an input by setting the GPIO_SETUP bits in the interrupt configuration register to 01. See GPIO section for more information on how to configure the GPIO. Enable the GPIO interrupt by setting the GPIO_INT_EN bit in Register 0x007 to 1, or disable by clearing this bit to 0. The GPIO status bit in the CDC conversion completion register reflects the status of the GPIO interrupt. This bit is set to 1 when the GPIO has triggered INT. The bit is cleared on read back from the register, provided the condition that caused the interrupt has gone away. The GPIO interrupt can be set to trigger on a rising edge, falling edge, high level, or low level at the GPIO input pin. Table 11 shows how the settings of the GPIO_INPUT_CONFIG bits in the interrupt configuration register affect the behavior of INT. Figure 29 to Figure 32 show how the interrupt output is cleared on a read from the CDC conversion completion register.
Rev. PrD | Page 22 of 64
05702-027
Preliminary Technical Data
1 SERIAL READ GPIO INPUT HIGH WHEN REGISTER IS READBACK GPIO INPUT
AD7142/AD7142-1
1 SERIAL READ BACK GPIO INPUT LOW WHEN REGISTER IS READBACK GPIO INPUT
INT OUTPUT
INT OUTPUT
GPIO INPUT LOW WHEN REGISTER IS READBACK GPIO INPUT
GPIO INPUT HIGH WHEN REGISTER IS READBACK GPIO INPUT
INT OUTPUT
INT OUTPUT
Figure 29. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00
05702-028
NOTES 1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT
NOTES 1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT
Figure 31. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 10
1 SERIAL READ BACK GPIO INPUT HIGH WHEN REGISTER IS READBACK GPIO INPUT
1 SERIAL READ BACK GPIO INPUT LOW WHEN REGISTER IS READBACK GPIO INPUT
INT OUTPUT
INT OUTPUT
GPIO INPUT LOW WHEN REGISTER IS READBACK
GPIO INPUT HIGH WHEN REGISTER IS READBACK GPIO INPUT
GPIO INPUT INT OUTPUT
INT OUTPUT
05702-029
NOTES 1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT
NOTES 1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT
Figure 30. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01
Figure 32. INT Output Controlled by the GPIO Input Example, GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11
Rev. PrD | Page 23 of 64
05702-031
05702-030
AD7142/AD7142-1 OUTPUTS
EXCITATION SOURCE
The excitation source on board the AD7142 is as square wave source with a frequency of 240 kHz. This excitation source forms the capacitance field between the transmitter and receiver in the external capacitance sensor PCB. The source is output from the AD7142 on two pins, the SRC pin and the SRC pin (outputs an inverted version of the source square wave). The SRC signal offsets large external sensor capacitances. In current applications, SRC is not used. The source output can be disabled from both output pins separately by writing to the control register (Address 0x000). Setting Bit 12 in this register to 1 disables the source output on the SRC pin. Setting Bit 13 in this register to 1 disables the inverted source output on the SRC pin.
Preliminary Technical Data
GPIO
The AD7142 has one GPIO pin, Pin 26. It can be configured as an input or an output. The GPIO_SETUP bits in the interrupt configuration register determine how the GPIO pin is configured. Table 12. GPIO_SETUP Bits
GPIO_SETUP 00 01 10 11 GPIO Configuration GPIO disabled Input Output low Output high
When the GPIO is configured as an output, the voltage level on the pin is set to either a low level or a high level, as defined by the GPIO_SETUP bits, shown in Table 12. When the GPIO is configured as an input, the GPIO_INPUT_CONFIGURATON bits in the interrupt configuration register determine the response of the AD7142 to a signal on the GPIO pin. The GPIO can be configured as either active high or active low, as well as either edge triggered or level triggered, as listed in Table 13. Table 13. GPIO_INPUT_CONFIGURATION Bits
GPIO_INPUT_CONFIGURATION 00 01 10 11 GPIO Configuration Triggered on negative level (active low) Triggered on positive edge (active high) Triggered on negative edge (active low) Triggered on positive level (active high)
CSHIELD OUTPUT
To prevent leakage from the external capacitance sensors, the sensor traces are shielded. The AD7142 has a voltage output that can be used as the potential for any shield traces, CSHIELD. The CSHIELD voltage is equal to VDD/2. The CSHIELD potential is derived from the output of the AD7142 internal amplifier, and is of equal potential to the CIN input lines. Because the shield is at the same potential as the sensor traces, no leakage to ground occurs. To eliminate any ringing on the CSHIELD output, connect a 10 nF capacitor between the CSHIELD pin and ground. CSHIELD is connected to layer three on a four-layer sensor PCB to provide shielding for the sensors. On a two-layer PCB construction, CSHIELD is used in place of a ground plane around the sensors, on both layers of the PCB. Figure 33 shows how the sensor traces are shielded by running traces connected to the shield potential around the sensor traces.
When GPIO is configured as an input, it triggers the interrupt output on the AD7142. Table 11 lists the interrupt output behavior for each of the GPIO configuration setups.
AD7142
SENSOR PCB CSHIELD
10nF
05702-032
Figure 33. Shielding the Sensor Traces
Rev. PrD | Page 24 of 64
Preliminary Technical Data SERIAL INTERFACE
The AD7142 is available with an SPI serial interface. The AD7142-1 is available with an I2C interface. Both parts are exactly the same, with the exception of the serial interface.
AD7142/AD7142-1
Bits[15:11] of the command word must be set to 11100 to successfully begin a bus transaction. Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a write. Bits[9:0] contain the target register address. When reading or writing to more than one register, this address indicates the address of the first register to be written to or read from.
SPI INTERFACE
The AD7142 has a 4-wire serial peripheral interface (SPI). The SPI has a data input pin (SDI) for inputting data to the device, a data output pin (SDO) for reading data back from the device, and a data clock pin (SCLK) for clocking data into and out of the device. A chip select pin (CS) enables or disables the serial interface. CS is required for correct operation of the SPI interface. Data is clocked out of the AD7142 on the negative edge of SCLK, and data is clocked into the device on the positive edge of SCLK.
Writing Data
Data is written to the AD7142 in 16-bit words. The first word written to the device is the command word, with the read/write bit set to 0. The master then supplies the 16-bit input data-word on the SDI line. The AD7142 clocks the data into the register addressed in the command word. If there is more than one word of data to be clocked in, the AD7142 automatically increments the address pointer, and clock the next data-word into the next register. The AD7142 continues to clock in data on the SDI line until either the master finishes the write transition by pulling CS high, or until the address pointer reaches its maximum value. The AD7142 address pointer does not wrap around. When it reaches its maximum value, any data provided by the master on the SDI line is ignored by the AD7142.
SPI Command Word
All data transactions on the SPI bus begin with the master taking CS low and sending out the command word. This indicates to the AD7142 whether the transaction is a read or a write, and gives the address of the register from which to begin the data transfer. Table 14. SPI Command Word
15 1 1 1 0 0 10 R/W 9 Register Address
16-BIT COMMAND WORD ENABLE WORD SDI CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4
0
16-BIT DATA CW 2 CW 1 CW 0 D15 D14 D13 D2 D1 D0
CW 3
t2
SCLK 1 2 t3 3 4 5
t4
6 7 8
t5
9 10 11 12 13 14 15 16 17 18 19 30 31 32
t1
CS
t8
Figure 34. Single Register Write SPI Timing
Rev. PrD | Page 25 of 64
05702-033
NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA. 3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
AD7142/AD7142-1
16-BIT COMMAND WORD ENABLE WORD SDI
CW 15 CW 14 CW 13 CW 12 CW 11
Preliminary Technical Data
DATA FOR STARTING REGISTER ADDRESS
CW 1 CW 0 D15 D14 D1 D0 D15
R/W
CW 10 CW 9 CW 8
STARTING REGISTER ADDRESS
CW 7 CW 6 CW 5 CW 4 CW 3 CW 2
DATA FOR NEXT REGISTER ADDRESS
D14 D1 D0 D15
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
47
48
49
CS NOTES 1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. 5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 0 (R/W) CW[9:0] = [AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0] (STARTING MSB JUSTIFIED REG IST ER ADDRESS )
Figure 35. Sequential Register Write SPI Timing
16-BIT COMMAND WORD ENABLE WORD SDI CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 X X X X X X
t2
SCLK 1 2 3 4 5
t4
6 7 8
t5
9 10 11 12 13 14 15 16 17 18 19 30 31 32
t1
CS
t3
t8
t6
SDO XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14 D13 D2 D1
t7
D0 XXX
16-BIT READ BACK DATA NOTES 1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5-BITS FOR ENABLE WORD, 1 BIT FOR R/W AND 10-BITS FOR REGISTER ADDRESS. 3. THE REGISTER DATA WILL BE READ BACK ON THE SDO PIN. 4. X DENOTES DON'T CARE. 5. XXX DENOTES HIGH IMPEDANCE TRISTATE OUTPUT. 6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READ-BACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
Figure 36. Single Register Readback SPI Timing
Reading Data
A read transaction begins when the master writes the command word to the AD7142 with the read/write bit set to 1. The master then supplies 16 clock pulses per data-word to be read, and the AD7142 clocks out data from the addressed register on the SDO line. The first data-word is clocked out on the first falling edge of CS following the command word, as shown in Figure 36.
The AD7142 continues to clock out data on the SDO line provided the master continues to supply the clock signal on SCLK. The read transaction finishes when the master takes CS high. If the AD7142 address pointer reaches its maximum value, then the AD7142 repeatedly clocks out data from the addressed register. The address pointer does not wrap around.
Rev. PrD | Page 26 of 64
05702-035
05702-034
Preliminary Technical Data
16-BIT COMMAND WORD ENABLE WORD SDI CW 15 CW 14 CW 13 CW 12 CW 11 R/W CW 10 CW 9 CW 8 CW 7 REGISTER ADDRESS CW 6 CW 5 CW 4 CW 3 CW 2 CW 1 CW 0 X X X X X X
AD7142/AD7142-1
X
X
X
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
47
48
49
CS
SDO
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
XXX XXX XXX
XXX XXX XXX
D15
D14
D1
D0
D15
D14
D1
D0
D15
READ BACK DATA FOR STARTING REGISTER ADDRESS
READ BACK DATA FOR NEXT REGISTER ADDRESS
NOTES 1. MULTIPLE REGISTERS MAY BE READ BACK CONTINUOUSLY. 2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5-BITS FOR ENABLE WORD, 1 BIT FOR R/W AND 10-BITS FOR REGISTER ADDRESS. 3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN. 4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK. 5. X DENOTES DON'T CARE. 6. XXX DENOTES HIGH IMPEDANCE TRISTATE OUTPUT. 7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READ-BACK OPERATION: CW[15:11] = 11100 (ENABLE WORD) CW[10] = 1 (R/W) CW[9:0] = AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 (STARTING MSB JUSTIFIED REGISTER ADDRESS)
Figure 37. Sequential Register Readback SPI Timing
I2C INTERFACE
The AD7142-1 supports the JEDEC industry standard 2-wire I2C serial interface protocol. The two wires associated with the I2C timing are the SCLK and the SDA inputs. The SDA is an I/O pin that allows both register write and register readback operations. The AD7142-1 is always a slave device on the I2C serial interface bus. It has a 7-bit device address, Address 0101 1XX. The lower two bits are set by tying the Add0 and Add1 pins high or low. The AD7142-1 responds when the master device sends its device address over the bus. The AD7142-1 cannot initiate data transfers on the bus. Table 15.AD7142-1 I2C Device Address
ADD1 0 0 1 1 ADD0 0 1 0 1 I2C Address 0101 100 0101 101 0101 110 0101 111
2.
All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit that determines the direction of the data transfer. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices on the bus now remain idle while the selected device waits for data to be read from, or written to it. If the R/W bit is a zero, the master writes to the slave device. If the R/W bit is a one, the master reads from the slave device. Data is sent over the serial bus in a sequence of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, since a low-to-high transition when the clock is high can be interpreted as a stop signal. The number of data bytes transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes are read or written, a stop condition is established. A stop condition is defined by a low-to-high transition on SDA while SCLK remains high. If the AD7142 encounters a stop condition, it returns to its idle condition, and the address pointer resets to Address 0x00.
3.
Data Transfer
1. Data is transferred over the I2C serial interface in 8-bit bytes. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCLK, remains high. This indicates that an address/data stream follows. 4.
Rev. PrD | Page 27 of 64
05702-036
AD7142/AD7142-1
START AD7142 DEVICE ADDRESS SDA DEV A6 DEV A5 DEV A4 DEV A3 DEV DEV A2 A1 DEV A0 R/W ACK REGISTER ADDRESS[A15:A8] A15 A14 A9 A8
Preliminary Technical Data
REGISTER ADDRESS[A7:A0] ACK A7 A6 A1 A0
t1
SCLK 1 2 3 4 5 6
t3
7 8 9 10 11 16 17 18 19 20 25 26
t2
STOP REGISTER DATA[D15:D8] ACK D15 D14 D9 D8 ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 ACK START
t8
AD7142 DEVICE ADDRESS DEV A6 DEV A5 DEV A4
t4
27 28 29 34 35 36 37
t5
38 43 44 45
t6
46
t7
1 2 3
NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH TO LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW TO HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X ARE DON'T CARES. 4. 16-BIT REGISTER ADDRESS[A15:A0] = [X X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0], WHERE X ARE DON'T CARES. 5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE AWAYS SEPERATED BY A LOW ACK BIT. 6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPERATED BY A LOW ACK BIT.
Figure 38. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
The process for writing to the AD7142-1 over the I2C bus is shown in Figure 38 and Figure 40. The device address is sent over the bus followed by the R/W bit set to 0. This is followed by two bytes of data that contain the 10-bit address of the internal data register to be written. The upper and lower register address bytes are shown in Table 16. Note that Bit 7 to Bit 2 in the upper address byte are don't cares. The address is contained in the 10 LSBs of the register address bytes. Table 16. AD7142-1 Internal Register I2C Addressing: Register Address Upper Byte
7 X 6 X 5 X 4 X 3 X 2 X 1 Register Address Bit 9 0 Register Address Bit 8
Any data written to the AD7142-1 after the address pointer has reached its maximum value is discarded. All registers on the AD7142-1 are 16-bit. Two consecutive 8-bit data bytes are combined and written to the 16-bit registers. To avoid errors, all writes to the device must contain an even number of data bytes. To finish the transaction, the master generates a stop condition on SDO, or generates a repeat start condition if the master is to maintain control of the bus.
Reading Data over the I2C Bus
To read from the AD7142-1, the address pointer must first be set to the address of the required internal register. The master performs a write transaction, and writes to the AD7142-1 to set the address pointer. The master then outputs a repeat start condition to keep control of the bus, or if this is not possible, ends the write transaction with a stop condition. A read transaction is initiated, with the R/W bit set to 1. The AD7142-1 supplies the upper eight bits of data from the addressed register in the first readback byte, followed by the lower eight bits in the next byte. This is shown in Figure 39 and Figure 40. Because the address pointer automatically increases after each read, the AD7142-1 continues to output readback data until the master puts a no acknowledge and stop condition on the bus. If the address pointer reaches its maximum value, and the master continues to read from the part, the AD7142-1 repeatedly sends data from the last register addressed.
Table 17. AD7142-1 Internal Register I2C Addressing: Register Address Lower Byte
7 Reg Add Bit 7 6 Reg Add Bit 6 5 Reg Add Bit 5 4 Reg Add Bit 4 3 Reg Add Bit 3 2 Reg Add Bit 2 1 Reg Add Bit 1 0 Reg Add Bit 0
The third data byte contains the eight MSBs of the data to be written to the internal register. The fourth byte of data contains the eight LSBs of data to be written to the internal register. The AD7142-1 address pointer register automatically increments after each write. This allows the master to sequentially write to all registers on the AD7142-1 in the same write transaction. However, the address pointer does not wrap around after the last address.
Rev. PrD | Page 28 of 64
05702-037
Preliminary Technical Data
START AD7142 DEVICE ADDRESS SDA DEV A6 DEV A5 DEV A4 DEV A3 DEV DEV A2 A1 DEV A0 R/W ACK REGISTER ADDRESS[A15:A8] A15 A14 A9 A8 ACK A7
AD7142/AD7142-1
REGISTER ADDRESS[A7:A0] A6 A1 A0 ACK
t1
SCLK 1 2 3 4 5 6
t3
7 8 9 10 11 16 17 18 19 20 25 26 27
t2
P SR DEV A6 USING REPEATED START 28 29 30 34 AD7142 DEVICE ADDRESS DEV A5 DEV A1 DEV A0 R/W ACK D7 REGISTER DATA[D7:D0] D6 D1 D0 NACK
t8
AD7142 DEVICE ADDRESS DEV A6 DEV A5 DEV A4
t4
35 36 37 38
t5
39 44 45 46
t6
t7
1 2 3
P
S DEV A6
AD7142 DEVICE ADDRESS DEV A5 DEV A1 DEV A0 R/W ACK D7
REGISTER DATA[D7:D0] D6 D1 D0 NACK
P
SEPERATE READ AND WRITE TRANSACTIONS 28 29 30 34
t4
35 36 37 38
t5
39 44 45 46
Figure 39. Example of I2C Timing for Single Register Readback Operation
WRITE
ACK ACK ACK ACK ACK
S
6-BIT DEVICE ADDRESS W
REGISTER ADDR [15:8]
REGISTER ADDR [7:0]
WRITE DATA HIGH BYTE [15:8]
WRITE DATA LOW BYTE [7:0]
WRITE DATA HIGH BYTE [15:8]
WRITE DATA LOW BYTE [7:0]
ACK
P
READ (USING REPEATED START)
ACK ACK ACK SR R ACK ACK
S
6-BIT DEVICE ADDRESS W
REGISTER ADDR HIGH BYTE
REGISTER ADDR LOW BYTE
6-BIT DEVICE ADDRESS
READ DATA HIGH BYTE [15:8]
READ DATA LOW BYTE [7:0]
READ DATA HIGH BYTE [15:8]
ACK
READ DATA NACK P LOW BYTE [7:0]
READ (WRITE TRANSACITON SETS UP REGISTER ADDRESS)
ACK ACK ACK R ACK ACK
S
6-BIT DEVICE ADDRESS W
REGISTER ADDR HIGH BYTE
REGISTER ADDR LOW BYTE
P
S 6-BIT DEVICE ADDRESS
READ DATA HIGH BYTE [15:8]
READ DATA LOW BYTE [7:0]
READ DATA HIGH BYTE [15:8]
ACK
READ DATA NACK P LOW BYTE [7:0]
05702-039
OUTPUT FROM MASTER OUTPUT FROM AD7142
S = START BIT P = STOP BIT SR = REPEATED START BIT
ACK = ACKNOWLEDGE BIT NACK = ACKNOWLEDGE BIT
Figure 40. Example of Sequential I2C Write and Readback Operation
VDRIVE INPUT
The supply voltage to all pins associated with both the I2C and SPI serial interfaces (SDO, SDI, SCLK, SDA, and CS) is separate from the main VCC supply and is connected to the VDRIVE pin.
This allows the AD7142 to be connected directly to processors whose supply voltage is less than the minimum operating voltage of the AD7142 without the need for external levelshifters. The VDRIVE pin can be connected to voltage supplies as low as 1.6 V and as high as VCC.
Rev. PrD | Page 29 of 64
05702-038
NOTES 1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH TO LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 2. A STOP CONDITION AT THE END IS DEFINED AS A LOW TO HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH. 3. THE MASTER GENERATES THE NACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WNAT ADDITIONAL DATA. 4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARES. 5. 16-BIT REGISTER ADDRESS[A15:A0] = [X X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0], WHERE THE UPPER LSB X 's ARE DON'T CARES. 6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE AWAYS SEPERATED BY A LOW ACK BIT. 7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPERATED BY A LOW ACK BIT. 8. THE R/W BIT IS SET TO A "1" TO INDICATE A READBACK OPERATION.
AD7142/AD7142-1 PCB DESIGN GUIDELINES
CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS
Table 18.
Parameter Distance from Edge of Any Sensor to Edge of Metal Object Distance Between Sensor Edges 1 Distance Between Bottom of Sensor Board and Controller Board or Metal Casing 2 (4-Layer, 2-Layer And Flex Circuit)
1
Preliminary Technical Data
Symbol D1 D2 = D3 = D4 D5
Min 1.0 0
Typ
Max
1.0
Unit mm mm mm
The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user's finger positioning and handling. Adjacent sensors, with 0 minimum space between them, are implemented differentially. 2 The 1.0 mm specification is meant to prevent any direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling from the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main controller board as shown in Figure 43.
CHIP SCALE PACKAGES
METAL OBJECT
CAPACITIVE SENSOR PRINTED CIRCUIT 8-WAY SWITCH
The lands on the chip scale package (CP-32-3) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width. Center the land on the pad to maximize the solder joint size. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. To avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the inner edges of the land pattern on the printed circuit board. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. Connect the printed circuit board thermal pad to GND.
D4 SLIDER
BUTTONS
D3
D2
D1
05702-045
Figure 41. Capacitive Sensor Board Mechanicals Top View
CAPACITIVE SENSOR BOARD D5 GROUNDED METAL SHIELD
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
Figure 42. Capacitive Sensor Board Mechanicals Side View
CAPACITIVE SENSOR BOARD D5 CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
05702-047
Figure 43. Capacitive Sensor Board with Grounded Shield
Rev. PrD | Page 30 of 64
05702-046
Preliminary Technical Data POWER-UP SEQUENCE
When the AD7142 is powered up, the following sequence is recommended: 1. 2. 3. Turn on the power supplies to the AD7142. Load all of the required Bank 2 configuration registers. Load Bank 1 registers at Address 0x000 through Address 0x004 (except Register Address 0x001 Bits[11:0]) and Register Address 0x045 to configure the AD7142. Load Bank 1 registers at Address 0x005 through Address 0x007. This enables the interrupt operation. 6. 5.
AD7142/AD7142-1
Set calibration enable bits for each conversion stage, Register Address 0x001 Bits[11:0]. Wait for three interrupt cycles. After the third interrupt, valid data is available in the AD7142 registers. Read back either the CDC conversion limit or CDC conversion completion registers to reset the INT output as explained in the Interrupt Output section. Repeat Step 5 every time INT is asserted.
7.
4.
DVCC = AVCC = VDRIVE = 3V POWER SUPPLIES 0V 1 2 SERIAL WRITES 3 4 5 6
tCONV
INT (OUTPUT) FIRST CONVERSION SECOND CONVERSION
05702-040
Figure 44. Recommended Start-Up Sequence
Rev. PrD | Page 31 of 64
AD7142/AD7142-1 TYPICAL APPLICATION CIRCUITS
VCC
Preliminary Technical Data
VDRIVE 10k
32
CIN1 31
CIN0 30
VREF- 29
VREF+ 28
TEST 27
GPIO 26
25
CIN2
SENSOR PCB LAYER 1
1 CIN3 2
INT CS 24 SCLK 23 SDI 22
INT SS SCK MOSI MISO
HOST WITH SPI INTERFACE
CIN4
SENSOR PCB LAYER 2
BUTTONS
SLIDER
3 CIN5 4 CIN6 5 CIN7 6 CIN8 7 CIN9
13 AVCC 15 SRC
AD7142
SDO 21 VDRIVE 20 DGND2 19
VHOST
1.8V
14 AGND 10 CIN12 11 CIN13
8-WAY SWITCH
8 CIN10
12 CSHIELD
DGND1 18 DVCC 17 SRC
16
CIN11
9
VCC 2.7V-3.6V 0.1F 1F-10F (OPTIONAL)
10nF
05702-041
Figure 45. Typical Application Circuit with SPI Interface
VDRIVE VCC 10k VDRIVE 10k
32
CIN1 31
CIN0 30
VREF- 29
VREF+ 28
TEST 27
GPIO 26
25
CIN2
1 CIN3 2 CIN4 3 CIN5
INT ADD1 24 SCLK 23 ADD0 22
INT
HOST WITH I2C INTERFACE
SCK
SENSOR PCB L AYER 2 BUTTON
4 CIN6
AD7142-1
SDA 21 VDRIVE 20 DGND2 19
SDO
SLIDER
5 CIN7 6 CIN8
BUTTON
14 AGND
10 CIN12
11 CIN13
13 AVCC
15 SRC
8-WAY SWITCH
12 CSHIELD
7 CIN9 8 CIN10
DGND1 18 DVCC 17 SRC
16
CIN11
9 SENSOR PCB LAYER 1
VCC 2.7V-3.6V 0.1F 1F-10F (OPTIONAL)
10nF
05702-042
Figure 46. Typical Application Circuit with I2C Interface
Rev. PrD | Page 32 of 64
Preliminary Technical Data REGISTER MAP
The AD7142 address space is divided into three different register banks, referred to as Register Bank 1, Register Bank 2, and Register Bank 3. Figure 47 illustrates the division of these three banks. Register Bank 1 contains setup and conversion control registers, interrupt configuration registers, and CDC conversion limit and completion registers. Register Bank 1 also contains the 16-bit ADC raw data for all 12 conversion stages and the AD7142 device ID register. Register Bank 2 contains the conversion stage configuration registers used for uniquely configuring the CIN inputs for each
AD7142/AD7142-1
conversion stage. Initialize the Bank 2 configuration registers immediately after power-up to obtain valid CDC conversion result data. Register Bank 3 contains the results of each conversion stage. These registers automatically update at the end of each conversion sequence. Although these registers are primarily used by the AD7142 internal data processing, they are accessible by the host processor for additional external data processing, if desired. Default values are undefined for Register Bank 2 and Register Bank 3 until after power up and configuration of Register Bank 2.
REGISTER BANK 1 ADDR 0x000 ADDR 0x001 CALIBRATION AND SET UP (4 REGISTERS) ADDR 0x005
24 REGISTERS
REGISTER BANK 2 ADDR 0x080 ADDR 0x088 ADDR 0x090 ADDR 0x098 ADDR 0x0A0
96 REGISTERS
REGISTER BANK 3 ADDR 0x0E0 ADDR 0x088 ADDR 0x090 ADDR 0x098 ADDR 0x0A0
432 REGISTERS
SET UP CONTROL (1 REGISTER)
STAGE 0 CONFIGURATION (8 REGISTERS) STAGE 1 CONFIGURATION (8 REGISTERS) STAGE 2 CONFIGURATION (8 REGISTERS) STAGE 3 CONFIGURATION (8 REGISTERS) STAGE 4 CONFIGURATION (8 REGISTERS) STAGE 5 CONFIGURATION (8 REGISTERS)
STAGE 0 RESULTS (36 REGISTERS) STAGE 1 RESULTS (36 REGISTERS) STAGE 2 RESULTS (36 REGISTERS) STAGE 3 RESULTS (36 REGISTERS) STAGE 4 RESULTS (36 REGISTERS) STAGE 5 RESULTS (36 REGISTERS)
INTERRUPT CONFIGURATION (3 REGISTERS) CDC CONVERSION LIMIT (2 REGISTERS) CDC CONVERSION COMPLETION (1 REGISTER) CDC 16-BIT CONVERSION DATA (12 REGISTERS)
ADDR 0x008 ADDR 0x00A ADDR 0x00B
ADDR 0x0A8 ADDR 0x0B0 ADDR 0x0B8 ADDR 0x0C0 ADDR 0x0C8 ADDR 0x0D0 ADDR 0x0D8
ADDR 0x0A8 ADDR 0x0B0 ADDR 0x0B8 ADDR 0x0C0 ADDR 0x0C8 ADDR 0x0D0 ADDR 0x28F
STAGE 6 CONFIGURATION (8 REGISTERS) STAGE 7 CONFIGURATION (8 REGISTERS) STAGE 8 CONFIGURATION (8 REGISTERS) STAGE 9 CONFIGURATION (8 REGISTERS) STAGE 10 CONFIGURATION (8 REGISTERS) STAGE 11 CONFIGURATION (8 REGISTERS)
STAGE 6 RESULTS (36 REGISTERS) STAGE 7 RESULTS (36 REGISTERS) STAGE 8 RESULTS (36 REGISTERS) STAGE 9 RESULTS (36 REGISTERS) STAGE 10 RESULTS (36 REGISTERS) STAGE 11 RESULTS (36 REGISTERS)
05702-043
ADDR 0x017 DEVICE ID REGISTER ADDR 0x018 INVALID DO NOT ACCESS ADDR 0x042 PROXIMITY STATUS REGISTER INVALID DO NOT ACCESS ADDR 0x045 LOW POWER MODE SETTLING TIME REGISTER INVALID DO NOT ACCESS INV
ADDR 0x7F 0x7F0
Figure 47. Layout of Bank 1, Bank 2, and Bank 3 Registers
Rev. PrD | Page 33 of 64
AD7142/AD7142-1 DETAILED REGISTER DESCRIPTIONS
BANK 1 REGISTERS
All addresses and default values are expressed in hexadecimal. Table 19. Control Register Map
Address 000 Data Bit Content [1:0] Default Value 0 Type R/W Name POWER_MODE
Preliminary Technical Data
[3:2]
0
LP_CONV_DELAY
[7:4]
0
SEQUENCE_STAGE_NUM
[9:8]
0
DECIMATION
[10] [11]
0 0
SW_RESET INT_POL
[12]
0
EXCITATION_SOURCE
[13]
0
SRC
[15:14]
0
CDC_BIAS
Description Operating Modes 00 = full power mode (Normal operation, CDC conversions approximately every 36 ms) 01 = full shutdown mode (No CDC conversions) 10 = low power mode (Automatic wake up operation) 11 = Full Shutdown Mode (No CDC conversions) Low Power Mode Conversion Delay 00 = 100 ms 01 = 200 ms 10 = 300 ms 11 = 400 ms Number of Stages in Sequence (N + 1) 0000 = 1 conversion stage in sequence 0001 = 2 conversion stages in sequence ...... Maximum value = 1011 = 12 conversion stages per sequence ADC Decimation Factor 00 = decimate by 256 01 = decimate by 128 10 = decimate by 64 11 = decimate by 64 Software Reset Control (Self-Clearing) 1 = resets all registers to default values Interrupt Polarity Control 0 = active low 1 = active high Excitation Source Control for Pin 15 0 = enable output 1 = disable output Excitation Source Control for Pin 16 0 = enable output 1 = disable output CDC Bias Current Control 00 = normal operation 01 = normal operation + 20% 10 = normal operation + 35% 11 = normal operation + 50%
Rev. PrD | Page 34 of 64
Preliminary Technical Data
Table 20. CDC Conversion Control Register Map
Address 001 Data Bit Content [0] Default Value 0 Type R/W Name STAGE0_CAL_EN
AD7142/AD7142-1
Description STAGE0 Calibration Enable 0 = disable 1 = enable STAGE1 Calibration Enable 0 = disable 1 = enable STAGE2 Calibration Enable 0 = disable 1 = enable STAGE3 Calibration Enable 0 = disable 1 = enable STAGE4 Calibration Enable 0 = disable 1 = enable STAGE5 Calibration Enable 0 = disable 1 = enable STAGE6 Calibration Enable 0 = disable 1 = enable STAGE7 Calibration Enable 0 = disable 1 = enable STAGE8 Calibration Enable 0 = disable 1 = enable STAGE9 Calibration Enable 0 = disable 1 = enable STAGE10 Calibration Enable 0 = disable 1 = enable STAGE11 Calibration Enable 0 = disable 1 = enable Full Power Mode Skip Control 00 = skip 3 samples 01 = skip 7 samples 10 = skip 15 samples 11 = skip 31 samples Low Power Mode Skip Control 00 = use all samples 01 = skip 1 sample 10 = skip 2 samples 11 = skip 3 samples
[1]
0
STAGE1_CAL_EN
[2]
0
STAGE2_CAL_EN
[3]
0
STAGE3_CAL_EN
[4]
0
STAGE4_CAL_EN
[5]
0
STAGE5_CAL_EN
[6]
0
STAGE6_CAL_EN
[7]
0
STAGE7_CAL_EN
[8]
0
STAGE8_CAL_EN
[9]
0
STAGE9_CAL_EN
[10]
0
STAGE10_CAL_EN
[11]
0
STAGE11_CAL_EN
[13:12]
0
AVG_FP_SKIP
[15:14]
0
AVG_LP_SKIP
Rev. PrD | Page 35 of 64
AD7142/AD7142-1
Address 002 Data Bit Content [3:0] Default Value 0 Type R/W Name FF_SKIP_CNT
Preliminary Technical Data
Description Fast Filter Skip Control (N+1) 0000 = 1 conversion skipped in each stage 0001 = 2 conversions skipped in each stage ...... 1011 = max value = 12 conversions skipped in each stage Full Power Mode Proximity Period Low Power Mode Proximity Period Power Down Time Out Control 00 = 1.25 x (LP_PROXIMITY_CNT) 01 = 1.50 x (LP_PROXIMITY_CNT) 10 = 1.75 x (LP_PROXIMITY_CNT) 11 = 2.00 x (LP_PROXIMITY_CNT) Forced Calibration Control 0 = normal operation 1 = forces all conversion stages to recalibrate Conversion Reset Control (Self-Clearing) 0 = normal operation 1 = resets the conversion sequence back to STAGE0. Proximity Recalibration Level Proximity Detection Rate Slow Filter Update Level Full Power Mode Proximity Recalibration Time Control Low Power Mode Proximity Recalibration Time Control
[7:4] [11:8] [13:12]
F F 0
FP_PROXIMITY_CNT LP_PROXIMITY_CNT PWR_DOWN_TIMEOUT
[14]
0
FORCED_CAL
[15]
0
CONV_RESET
003
004
[7:0] [13:8] [15:14] [9:0] [15:10]
64 1 0 3FF 3F
R/W
R/W
PROXIMITY_RECAL_LVL PROXIMITY_DETECTION_RATE SLOW_FILTER_UPDATE_LVL FP_PROXIMITY_RECAL LP_PROXIMITY_RECAL
Table 21. Interrupt Configuration Register Map
Address 005 Data Bit Content [0] Default Value 0 Type R/W Name STAGE0_LOW_INT_EN Description STAGE0 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE1 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE2 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE3 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE4 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE5 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE6 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded
[1]
0
STAGE1_LOW_INT_EN
[2]
0
STAGE2_LOW_INT_EN
[3]
0
STAGE3_LOW_INT_EN
[4]
0
STAGE4_LOW_INT_EN
[5]
0
STAGE5_LOW_INT_EN
[6]
0
STAGE6_LOW_INT_EN
Rev. PrD | Page 36 of 64
Preliminary Technical Data
Address Data Bit Content [7] Default Value 0 Type Name STAGE7_LOW_INT_EN
AD7142/AD7142-1
Description STAGE7 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE8 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE9 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE10 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded STAGE11 Low Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 low reference is exceeded GPIO Setup 00 = disable GPIO pin 01 = configure GPIO as an input 10 = configure GPIO as an active low output 11 = configure GPIO as an active high output GPIO Input Configuration 00 = triggered on negative level 01 = triggered on positive edge 10 = triggered on negative edge 11 = triggered on positive level STAGE0 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE1 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE2 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE3 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE4 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE5 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE6 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE7 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded
[8]
0
STAGE8_LOW_INT_EN
[9]
0
STAGE9_LOW_INT_EN
[10]
0
STAGE10_LOW_INT_EN
[11]
0
STAGE11_LOW_INT_EN
[13:12]
0
GPIO_SETUP
[15:14]
0
GPIO_INPUT_CONFIG
006
[0]
0
R/W
STAGE0_HIGH_INT_EN
[1]
0
STAGE1_HIGH_INT_EN
[2]
0
STAGE2_HIGH_INT_EN
[3]
0
STAGE3_HIGH_INT_EN
[4]
0
STAGE4_HIGH_INT_EN
[5]
0
STAGE5_HIGH_INT_EN
[6]
0
STAGE6_HIGH_INT_EN
[7]
0
STAGE7_HIGH_INT_EN
Rev. PrD | Page 37 of 64
AD7142/AD7142-1
Address Data Bit Content [8] Default Value 0 Type Name STAGE8_HIGH_INT_EN
Preliminary Technical Data
Description STAGE8 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE9 Sensor Interrupt Low Limit Control 0 = interrupt source disabled 1 = INT asserted if STAGE10_LOW is exceeded STAGE10 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded STAGE11 High Interrupt Enable 0 = interrupt source disabled 1 = INT asserted if STAGE0 high reference is exceeded Set Unused Register Bits = 0 STAGE0 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE0 conversion STAGE1 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE1 conversion STAGE2 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE2 conversion STAGE3 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE3 conversion STAGE4 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE4 conversion STAGE5 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE5 conversion STAGE6 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE6 conversion STAGE7 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE7 conversion STAGE8 Conversion Complete Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE8 conversion STAGE9 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE9 conversion STAGE10 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE10 conversion STAGE11 Conversion Interrupt Control 0 = interrupt source disabled 1 = INT asserted at completion of STAGE11 conversion
[9]
0
STAGE9_HIGH_INT_EN
[10]
0
STAGE10_HIGH_INT_EN
[11]
0
STAGE11_HIGH_INT_EN
007
[15:12] [0]
0
R/W
Unused STAGE0_COMPLETE_EN
[1]
0
STAGE1_COMPLETE_EN
[2]
0
STAGE2_COMPLETE_EN
[3]
0
STAGE3_COMPLETE_EN
[4]
0
STAGE4_COMPLETE_EN
[5]
0
STAGE5_COMPLETE_EN
[6]
0
STAGE6_COMPLETE_EN
[7]
0
STAGE7_COMPLETE_EN
[8]
0
STAGE8_COMPLETE_EN
[9]
0
STAGE9_COMPLETE_EN
[10]
0
STAGE10_COMPLETE_EN
[11]
0
STAGE11_COMPLETE_EN
Rev. PrD | Page 38 of 64
Preliminary Technical Data
Address Data Bit Content [12] Default Value 0 Type Name GPIO_INT_EN
AD7142/AD7142-1
Description Interrupt Control when GPIO Input Pin Changes Level 0 = disabled 1 = enabled Set Unused Register Bits = 0
[15:13]
Unused
Table 22. CDC Low Limit Status Register Map 1
Address 008 Data Bit Content [0] Default Value 0 Type R Name STAGE0_LOW_LIMIT Description STAGE0 CDC Conversion Low Limit Result 1 = indicates STAGE0_OFFSET_LOW value was exceeded STAGE1 CDC Conversion Low Limit Result 1 = indicates STAGE1_OFFSET_LOW value was exceeded STAGE2 CDC Conversion Low Limit Result 1 = indicates STAGE2_OFFSET_LOW value was exceeded STAGE3 CDC Conversion Low Limit Result 1 = indicates STAGE3_OFFSET_LOW value was exceeded STAGE4 CDC Conversion Low Limit Result 1 = indicates STAGE4_OFFSET_LOW value was exceeded STAGE5 CDC Conversion Low Limit Result 1 = indicates STAGE5_OFFSET_LOW value was exceeded STAGE6 CDC Conversion Low Limit Result 1 = indicates STAGE6_OFFSET_LOW value was exceeded STAGE7 CDC Conversion Low Limit Result 1 = indicates STAGE7_OFFSET_LOW value was exceeded STAGE8 CDC Conversion Low Limit Result 1 = indicates STAGE8_OFFSET_LOW value was exceeded STAGE9 CDC Conversion Low Limit Result 1 = indicates STAGE9_OFFSET_LOW value was exceeded STAGE10 CDC Conversion Low Limit Result 1 = indicates STAGE10_OFFSET_LOW value was exceeded STAGE11 CDC Conversion Low Limit Result 1 = indicates STAGE11_OFFSET_LOW value was exceeded Set Unused Register Bits = 0
[1]
0
STAGE1_LOW_LIMIT
[2]
0
STAGE2_LOW_LIMIT
[3]
0
STAGE3_LOW_LIMIT
[4]
0
STAGE4_LOW_LIMIT
[5]
0
STAGE5_LOW_LIMIT
[6]
0
STAGE6_LOW_LIMIT
[7]
0
STAGE7_LOW_LIMIT
[8]
0
STAGE8_LOW_LIMIT
[9]
0
STAGE9_LOW_LIMIT
[10]
0
STAGE10_LOW_LIMIT
[11]
0
STAGE11_LOW_LIMIT
[15:12]
1
Unused
Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Rev. PrD | Page 39 of 64
AD7142/AD7142-1
Table 23.CDC High Limit Status 1
Address 009 Data Bit Content [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] Default Value 0 0 0 0 0 0 0 0 0 0 0 Type R Name STAGE0_HIGH_LIMIT STAGE1_HIGH_LIMIT STAGE2_HIGH_LIMIT STAGE3_HIGH_LIMIT STAGE4_HIGH_LIMIT STAGE5_HIGH_LIMIT STAGE6_HIGH_LIMIT STAGE7_HIGH_LIMIT STAGE8_HIGH_LIMIT STAGE9_HIGH_LIMIT STAGE10_HIGH_LIMIT
Preliminary Technical Data
Description STAGE0 CDC Conversion High Limit Result 1 = indicates STAGE0_OFFSET_HIGH value was exceeded STAGE1 CDC Conversion High Limit Result 1 = indicates STAGE1_OFFSET_HIGH value was exceeded Stage2 CDC Conversion High Limit Result 1 = indicates STAGE2_OFFSET_HIGH value was exceeded STAGE3 CDC Conversion High Limit Result 1 = indicates STAGE3_OFFSET_HIGH value was exceeded STAGE4 CDC Conversion High Limit Result 1 = indicates STAGE4_OFFSET_HIGH value was exceeded STAGE5 CDC Conversion High Limit Result 1 = indicates STAGE5_OFFSET_HIGH value was exceeded STAGE6 CDC Conversion High Limit Result 1 = indicates STAGE6_OFFSET_HIGH value was exceeded STAGE7 CDC Conversion Low Limit Result 1 = indicates STAGE7_OFFSET_HIGH value was exceeded STAGE8 CDC Conversion High Limit Result 1 = indicates STAGE8_OFFSET_HIGH value was exceeded STAGE9 CDC Conversion High Limit Result 1 = indicates STAGE9_OFFSET_HIGH value was exceeded STAGE10 CDC Conversion High Limit Result 1 =indicates STAGE10_OFFSET_HIGH value was exceeded STAGE11 CDC Conversion High Limit Result 1 = indicates STAGE11_OFFSET_HIGH value was exceeded Set Unused Register Bits = 0
[11]
0
STAGE11_HIGH_LIMIT
[15:12]
1
Unused
Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Rev. PrD | Page 40 of 64
Preliminary Technical Data
Table 24. CDC Conversion Completion Register Map 1
Address 00A Data Bit Content [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [15:13]
1
AD7142/AD7142-1
Name STAGE0_COMPLETE_STATUS STAGE1_COMPLETE_STATUS STAGE2_COMPLETE_STATUS STAGE3_COMPLETE_STATUS STAGE4_COMPLETE_STATUS STAGE5_COMPLETE_STATUS STAGE6_COMPLETE_STATUS STAGE7_COMPLETE_STATUS STAGE8_COMPLETE_STATUS STAGE9_COMPLETE_STATUS STAGE10_COMPLETE_STATUS STAGE11_COMPLETE_STATUS GPIO_STATUS Unused Description STAGE0 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE1 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE2 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE3 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE4 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE5 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE6 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE7 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE8 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE9 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE10 Conversion Completion Status 1 = indicates STAGE0 conversion completed STAGE11 Conversion Completion Status 1 = indicates STAGE0 conversion completed GPIO Input Pin Status 1 = indicates level on GPIO pin has changed Set Unused Register Bits = 0
Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0
Type R
Registers self-clear to 0 after readback.
Rev. PrD | Page 41 of 64
AD7142/AD7142-1
Table 25. CDC 16-Bit Conversion Data Register Map
Address 00B 00C 00D 00E 00F 010 011 012 013 014 015 016 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value 0 0 0 0 0 0 0 0 0 0 0 0 Type R R R R R R R R R R R R Name STAGE0_CONV_DATA STAGE1_CONV_DATA STAGE2_CONV_DATA STAGE3_CONV_DATA STAGE4_CONV_DATA STAGE5_CONV_DATA STAGE6_CONV_DATA STAGE7_CONV_DATA STAGE8_CONV_DATA STAGE9_CONV_DATA STAGE10_CONV_DATA STAGE11_CONV_DATA
Preliminary Technical Data
Description STAGE0 CDC 16-Bit Conversion Data STAGE1 CDC 16-Bit Conversion Data STAGE2 CDC 16-Bit Conversion Data STAGE3 CDC 16-Bit Conversion Data STAGE4 CDC 16-Bit Conversion Data STAGE5 CDC 16-Bit Conversion Data STAGE6 CDC 16-Bit Conversion Data STAGE7 CDC 16-Bit Conversion Data STAGE8 CDC 16-Bit Conversion Data STAGE9 CDC 16-Bit Conversion Data STAGE10 CDC 16-Bit Conversion Data STAGE11 CDC 16-Bit Conversion Data
Table 26. Device ID Register Map
Address 017 Data Bit Content [3:0] [15:4] Default Value 2 E62 Type R R Name REVISION_CODE DEVICE_ID Description AD7142 Revision Code AD7142 Device ID = 110110100010
Table 27. Proximity Status Register
Address 042 Data Bit Content [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [15:0] Default Value 0 0 0 0 0 0 0 0 0 0 0 0 Type R R R R R R R R R R R R Name STAGE0_PROXIMITY_STATUS STAGE1_PROXIMITY_STATUS STAGE2_PROXIMITY_STATUS STAGE3_PROXIMITY_STATUS STAGE4_PROXIMITY_STATUS STAGE5_PROXIMITY_STATUS STAGE6_PROXIMITY_STATUS STAGE7_PROXIMITY_STATUS STAGE8_PROXIMITY_STATUS STAGE9_PROXIMITY_STATUS STAGE10_PROXIMITY_STATUS STAGE11_PROXIMITY_STATUS Unused Description STAGE0 Proximity Status Register 1 = indicates proximity has been detected on STAGE0 STAGE1 Proximity Status Register 1 = indicates proximity has been detected on STAGE1 STAGE2 Proximity Status Register 1 = indicates proximity has been detected on STAGE2 STAGE3 Proximity Status Register 1 = indicates proximity has been detected on STAGE3 STAGE4 Proximity Status Register 1 = indicates proximity has been detected on STAGE4 STAGE5 Proximity Status Register 1 = indicates proximity has been detected on STAGE5 STAGE6 Proximity Status Register 1 = indicates proximity has been detected on STAGE6 STAGE7 Proximity Status Register 1 = indicates proximity has been detected on STAGE7 STAGE8 Proximity Status Register 1 = indicates proximity has been detected on STAGE8 STAGE9 Proximity Status Register 1 = indicates proximity has been detected on STAGE9 STAGE10 Proximity Status Register 1 = indicates proximity has been detected on STAGE10 STAGE11 Proximity Status Register 1 = indicates proximity has been detected on STAGE11 Set Unused Register Bits = 0
Rev. PrD | Page 42 of 64
Preliminary Technical Data
Table 28. Low Power Mode Settling Time Register
Address 045 Data Bit Content [1:0] [14:2] [15:13] Default Value 0x3 0x240 0x0 Type R/W R/W R/W Name Unused--test bits Unused--test bits Low power mode settling time
AD7142/AD7142-1
Description Set Unused Register Bits = 11 Binary. Note that these bits always read back as 01 binary. Set Unused Register Bits = 0x240 These bits control the settling time of the ADC in low power mode. Each unit of delay is equivalent to one conversion time. Set to 0x2.
Rev. PrD | Page 43 of 64
AD7142/AD7142-1
BANK 2 REGISTERS
All address values are expressed in hexadecimal. Table 29. STAGE0 Configuration Register Map
Address 080 081 082 083 084 085 086 087 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE0_CIN(0:6)_SETUP STAGE0_CIN(7:13)_SETUP STAGE0_AFE_OFFSET STAGE0_SENSITIVITY STAGE0_OFFSET_LOW STAGE0_OFFSET_HIGH STAGE0_OFFSET_HIGH_CLAMP STAGE0_OFFSET_LOW_CLAMP
Preliminary Technical Data
Description STAGE0 CIN(0:6) Connection Set-Up (See Table 53) STAGE0 CIN(7:13) Connection Set-Up (See Table 54) STAGE0 AFE Offset Control (See Table 55) STAGE0 Sensitivity Control (See Table 56) STAGE0 Initial Offset Low Value STAGE0 Initial Offset High Value STAGE0 Offset High Clamp Value STAGE0 Offset Low Clamp Value
Table 30. STAGE1 Configuration Register Map
Address 088 089 08A 08B 08C 08D 08E 08F Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE1_CIN(0:6)_SETUP STAGE1_CIN(7:13)_SETUP STAGE1_AFE_OFFSET STAGE1_SENSITIVITY STAGE1_OFFSET_LOW STAGE1_OFFSET_HIGH STAGE1_OFFSET_HIGH_CLAMP STAGE1_OFFSET_LOW_CLAMP Description STAGE1 CIN(0:6) Connection Setup (See Table 53) STAGE1 CIN(7:13) Connection Setup (See Table 54) STAGE1 AFE Offset Control (See Table 55) STAGE1 Sensitivity Control (See Table 56) STAGE1 Initial Offset Low Value STAGE1 Initial Offset High Value STAGE1 Offset High Clamp Value STAGE1 Offset Low Clamp Value
Table 31. STAGE2 Configuration Register Map
Address 090 091 092 093 094 095 096 097 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE2_CIN(0:6)_SETUP STAGE2_CIN(7:13)_SETUP STAGE2_AFE_OFFSET STAGE2_SENSITIVITY STAGE2_OFFSET_LOW STAGE2_OFFSET_HIGH STAGE2_OFFSET_HIGH_CLAMP STAGE2_OFFSET_LOW_CLAMP Description STAGE2 CIN(0:6) Connection Setup (See Table 53) STAGE2 CIN(7:13) Connection Setup (See Table 54) STAGE2 AFE Offset Control (See Table 55) STAGE2 Sensitivity Control (See Table 56) STAGE2 Initial Offset Low Value STAGE2 Initial Offset High Value STAGE2 Offset High Clamp Value STAGE2 Offset Low Clamp Value
Table 32. STAGE3 Configuration Register Map
Address 098 099 09A 09B 09C 09D 09E 09F Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE3_CIN(0:6)_SETUP STAGE3_CIN(7:13)_SETUP STAGE3_AFE_OFFSET STAGE3_SENSITIVITY STAGE3_OFFSET_LOW STAGE3_OFFSET_HIGH STAGE3_OFFSET_HIGH_CLAMP STAGE3_OFFSET_LOW_CLAMP Description STAGE3 CIN(0:6) Connection Setup (See Table 53) STAGE3 CIN(7:13) Connection Setup (See Table 54) STAGE3 AFE Offset Control (See Table 55) STAGE3 Sensitivity Control (See Table 56) STAGE3 Initial Offset Low Value STAGE3 Initial Offset High Value STAGE3 Offset High Clamp Value STAGE3 Offset Low Clamp Value
Rev. PrD | Page 44 of 64
Preliminary Technical Data
Table 33. STAGE4 Configuration Register Map
Address 0A0 0A1 0A2 0A3 0A4 0A5 0A6 0A7 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE4_CIN(0:6)_SETUP STAGE4_CIN(7:13)_SETUP STAGE4_AFE_OFFSET STAGE4_SENSITIVITY STAGE4_OFFSET_LOW STAGE4_OFFSET_HIGH STAGE4_OFFSET_HIGH_CLAMP STAGE4_OFFSET_LOW_CLAMP
AD7142/AD7142-1
Description STAGE4 CIN(0:6) Connection Setup (See Table 53) STAGE4 CIN(7:13) Connection Setup (See Table 54) STAGE4 AFE Offset Control (See Table 55) STAGE4 Sensitivity Control (See Table 56) STAGE4 Initial Offset Low Value STAGE4 Initial Offset High Value STAGE4 Offset High Clamp Value STAGE4 Offset Low Clamp Value
Table 34. STAGE5 Configuration Register Map
Address 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE5_CIN(0:6)_SETUP STAGE5_CIN(7:13)_SETUP STAGE5_AFE_OFFSET STAGE5_SENSITIVITY STAGE5_OFFSET_LOW STAGE5_OFFSET_HIGH STAGE5_OFFSET_HIGH_CLAMP STAGE5_OFFSET_LOW_CLAMP Description STAGE5 CIN(0:6) Connection Setup (See Table 53) STAGE5 CIN(7:13) Connection Setup (See Table 54) STAGE5 AFE Offset Control (See Table 55) STAGE5 Sensitivity Control (See Table 56) STAGE5 Initial Offset Low Value STAGE5 Initial Offset High Value STAGE5 Offset High Clamp Value STAGE5 Offset Low Clamp Value
Table 35. STAGE6 Configuration Register Map
Address 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE6_CIN(0:6)_SETUP STAGE6_CIN(7:13)_SETUP STAGE6_AFE_OFFSET STAGE6_SENSITIVITY STAGE6_OFFSET_LOW STAGE6_OFFSET_HIGH STAGE6_OFFSET_HIGH_CLAMP STAGE6_OFFSET_LOW_CLAMP Description STAGE6 CIN(0:6) Connection Setup (See Table 53) STAGE6 CIN(7:13) Connection Setup (See Table 54) STAGE6 AFE Offset Control (See Table 55) STAGE6 Sensitivity Control (See Table 56) STAGE6 Initial Offset Low Value STAGE6 Initial Offset High Value STAGE6 Offset High Clamp Value STAGE6 Offset Low Clamp Value
Table 36. STAGE7 Configuration Register Map
Address 0B8 0B9 0BA 0BB 0BC 0BD 0BE 0BF Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE7_CIN(0:6)_SETUP STAGE7_CIN(7:13)_SETUP STAGE7_AFE_OFFSET STAGE7_SENSITIVITY STAGE7_OFFSET_LOW STAGE7_OFFSET_HIGH STAGE7_OFFSET_HIGH_CLAMP STAGE7_OFFSET_LOW_CLAMP Description STAGE7 CIN(0:6) Connection Setup (See Table 53) STAGE7 CIN(7:13) Connection Setup (See Table 54) STAGE7 AFE Offset Control (See Table 55) STAGE7 Sensitivity Control (See Table 56) STAGE7 Initial Offset Low Value STAGE7 Initial Offset High Value STAGE7 Offset High Clamp Value STAGE7 Offset Low Clamp Value
Rev. PrD | Page 45 of 64
AD7142/AD7142-1
Table 37. STAGE8 Configuration Register Map
Address 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE8_CIN(0:6)_SETUP STAGE8_CIN(7:13)_SETUP STAGE8_AFE_OFFSET STAGE8_SENSITIVITY STAGE8_OFFSET_LOW STAGE8_OFFSET_HIGH STAGE8_OFFSET_HIGH_CLAMP STAGE8_OFFSET_LOW_CLAMP
Preliminary Technical Data
Description STAGE8 CIN(0:6) Connection Setup (See Table 53) STAGE8 CIN(7:13) Connection Setup (See Table 54) STAGE8 AFE Offset Control (See Table 55) STAGE8 Sensitivity Control (See Table 56) STAGE8 Initial Offset Low Value STAGE8 Initial Offset High Value STAGE8 Offset High Clamp Value STAGE8 Offset Low Clamp Value
Table 38. STAGE9 Configuration Register Map
Address 0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE9_CIN(0:6)_SETUP STAGE9_CIN(7:13)_SETUP STAGE9_AFE_OFFSET STAGE9_SENSITIVITY STAGE9_OFFSET_LOW STAGE9_OFFSET_HIGH STAGE9_OFFSET_HIGH_CLAMP STAGE9_OFFSET_LOW_CLAMP Description STAGE9 CIN(0:6) Connection Setup (See Table 53) STAGE9 CIN(7:13) Connection Setup (See Table 54) STAGE9 AFE Offset Control (See Table 55) STAGE9 Sensitivity Control (See Table 56) STAGE9 Initial Offset LOW Value STAGE9 Initial Offset HIGH Value STAGE9 Offset High Clamp Value STAGE9 Offset Low Clamp Value
Table 39. STAGE10 Configuration Register Map
Address 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE10_CIN(0:6)_SETUP STAGE10_CIN(7:13)_SETUP STAGE10_AFE_OFFSET STAGE10_SENSITIVITY STAGE10_OFFSET_LOW STAGE10_OFFSET_HIGH STAGE10_OFFSET_HIGH_CLAMP STAGE10_OFFSET_LOW_CLAMP Description STAGE10 CIN(0:6) Connection Setup (See Table 53) STAGE10 CIN(7:13) Connection Setup (See Table 54) STAGE10 AFE Offset Control (See Table 55) STAGE10 Sensitivity Control (See Table 56) STAGE10 Initial Offset LOW Value STAGE10 Initial Offset HIGH Value STAGE10 Offset High Clamp Value STAGE10 Offset Low Clamp Value
Table 40. STAGE11 Configuration Register Map
Address 0D8 0D9 0DA 0DB 0DC 0DD 0DE 0DF Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE11_CIN(0:6)_SETUP STAGE11_CIN(7:13)_SETUP STAGE11_AFE_OFFSET STAGE11_SENSITIVITY STAGE11_OFFSET_LOW STAGE11_OFFSET_HIGH STAGE11_OFFSET_HIGH_CLAMP STAGE11_OFFSET_LOW_CLAMP Description STAGE11 CIN(0:6) Connection Setup (See Table 53) STAGE11 CIN(7:13) Connection Setup (See Table 54) STAGE11 AFE Offset Control (See Table 55) STAGE11 Sensitivity Control (See Table 56) STAGE11 Initial Offset LOW Value STAGE11 Initial Offset HIGH Value STAGE11 Offset High Clamp Value STAGE11 Offset Low Clamp Value
Rev. PrD | Page 46 of 64
Preliminary Technical Data
BANK 3 REGISTERS
All address values are expressed in hexadecimal. Table 41. STAGE0 Results Register Map
Address 0E0 0E1 0E2 0E3 0E4 0E5 0E6 0E7 0E8 0E9 0EA 0EB 0EC 0ED 0EE 0EF 0F0 0F1 0F2 0F3 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC 0FD 0FE 0FF 100 101 102 103 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE0_CONV_DATA STAGE0_FF_WORD0 STAGE0_FF_WORD1 STAGE0_FF_WORD2 STAGE0_FF_WORD3 STAGE0_FF_WORD4 STAGE0_FF_WORD5 STAGE0_FF_WORD6 STAGE0_FF_WORD7 STAGE0_SF_WORD0 STAGE0_SF_WORD1 STAGE0_SF_WORD2 STAGE0_SF_WORD3 STAGE0_SF_WORD4 STAGE0_SF_WORD5 STAGE0_SF_WORD6 STAGE0_SF_WORD7 STAGE0_SF_AMBIENT STAGE0_FF_AVG STAGE0_PEAK_DETECT_WORD0 STAGE0_PEAK_DETECT_WORD1 STAGE0_MAX_WORD0 STAGE0_MAX_WORD1 STAGE0_MAX_WORD2 STAGE0_MAX_WORD3 STAGE0_MAX_AVG STAGE0_HIGH_THRESHOLD STAGE0_MAX_TEMP STAGE0_MIN_WORD0 STAGE0_MIN_WORD1 STAGE0_MIN_WORD2 STAGE0_MIN_WORD3 STAGE0_MIN_AVG STAGE0_LOW_THRESHOLD STAGE0_MIN_TEMP Unused
AD7142/AD7142-1
Description STAGE0 CDC 16-Bit Conversion Data (Copy of data in STAGE0_CONV_DATA register) STAGE0 Fast FIFO WORD0 STAGE0 Fast FIFO WORD1 STAGE0 Fast FIFO WORD2 STAGE0 Fast FIFO WORD3 STAGE0 Fast FIFO WORD4 STAGE0 Fast FIFO WORD5 STAGE0 Fast FIFO WORD6 STAGE0 Fast FIFO WORD7 STAGE0 Slow FIFO WORD0 STAGE0 Slow FIFO WORD1 STAGE0 Slow FIFO WORD2 STAGE0 Slow FIFO WORD3 STAGE0 Slow FIFO WORD4 STAGE0 Slow FIFO WORD5 STAGE0 Slow FIFO WORD6 STAGE0 Slow FIFO WORD7 STAGE0 Slow FIFO Ambient Value STAGE0 Fast FIFO Average Value STAGE0 Peak FIFO WORD0 Value STAGE0 Peak FIFO WORD1 Value STAGE0 Maximum Value FIFO WORD0 STAGE0 Maximum Value FIFO WORD1 STAGE0 Maximum Value FIFO WORD2 STAGE0 Maximum Value FIFO WORD3 STAGE0 Average Maximum FIFO Value STAGE0 High Threshold Value STAGE0 Temporary Maximum Value STAGE0 Minimum Value FIFO WORD0 STAGE0 Minimum Value FIFO WORD1 STAGE0 Minimum Value FIFO WORD2 STAGE0 Minimum Value FIFO WORD3 STAGE0 Average Minimum FIFO Value STAGE0 Low Threshold Value STAGE0 Temporary Minimum Value
Rev. PrD | Page 47 of 64
AD7142/AD7142-1
Table 42. STAGE1 Results Register Map
Address 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F 120 121 122 123 124 125 126 127 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE1_CONV_DATA STAGE1_FF_WORD0 STAGE1_FF_WORD1 STAGE1_FF_WORD2 STAGE1_FF_WORD3 STAGE1_FF_WORD4 STAGE1_FF_WORD5 STAGE1_FF_WORD6 STAGE1_FF_WORD7 STAGE1_SF_WORD0 STAGE1_SF_WORD1 STAGE1_SF_WORD2 STAGE1_SF_WORD3 STAGE1_SF_WORD4 STAGE1_SF_WORD5 STAGE1_SF_WORD6 STAGE1_SF_WORD7 STAGE1_SF_AMBIENT STAGE1_FF_AVG STAGE1_CDC_WORD0 STAGE1_CDC_WORD1 STAGE1_MAX_WORD0 STAGE1_MAX_WORD1 STAGE1_MAX_WORD2 STAGE1_MAX_WORD3 STAGE1_MAX_AVG STAGE1_HIGH_THRESHOLD STAGE1_MAX_TEMP STAGE1_MIN_WORD0 STAGE1_MIN_WORD1 STAGE1_MIN_WORD2 STAGE1_MIN_WORD3 STAGE1_MIN_AVG STAGE1_LOW_THRESHOLD STAGE1_MIN_TEMP Unused
Preliminary Technical Data
Description STAGE1 CDC 16-Bit Conversion Data (Copy of data in STAGE1_CONV_DATA register) STAGE1 Fast FIFO WORD0 STAGE1 Fast FIFO WORD1 STAGE1 Fast FIFO WORD2 STAGE1 Fast FIFO WORD3 STAGE1 Fast FIFO WORD4 STAGE1 Fast FIFO WORD5 STAGE1 Fast FIFO WORD6 STAGE1 Fast FIFO WORD7 STAGE1 Slow FIFO WORD0 STAGE1 Slow FIFO WORD1 STAGE1 Slow FIFO WORD2 STAGE1 Slow FIFO WORD3 STAGE1 Slow FIFO WORD4 STAGE1 Slow FIFO WORD5 STAGE1 Slow FIFO WORD6 STAGE1 Slow FIFO WORD7 STAGE1 Slow FIFO Ambient Value STAGE1 Fast FIFO Average Value STAGE1 CDC FIFO WORD0 STAGE1 CDC FIFO WORD1 STAGE1 Maximum Value FIFO WORD0 STAGE1 Maximum Value FIFO WORD1 STAGE1 Maximum Value FIFO WORD2 STAGE1 Maximum Value FIFO WORD3 STAGE1 Average Maximum FIFO Value STAGE1 High Threshold Value STAGE1 Temporary Maximum Value STAGE1 Minimum Value FIFO WORD0 STAGE1 Minimum Value FIFO WORD1 STAGE1 Minimum Value FIFO WORD2 STAGE1 Minimum Value FIFO WORD3 STAGE1 Average Minimum FIFO Value STAGE1 Low Threshold Value STAGE1 Temporary Minimum Value
Rev. PrD | Page 48 of 64
Preliminary Technical Data
Table 43. STAGE2 Results Register Map
Address 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F 140 141 142 143 144 145 146 147 148 149 14A 14B Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE2_CONV_DATA STAGE2_FF_WORD0 STAGE2_FF_WORD1 STAGE2_FF_WORD2 STAGE2_FF_WORD3 STAGE2_FF_WORD4 STAGE2_FF_WORD5 STAGE2_FF_WORD6 STAGE2_FF_WORD7 STAGE2_SF_WORD0 STAGE2_SF_WORD1 STAGE2_SF_WORD2 STAGE2_SF_WORD3 STAGE2_SF_WORD4 STAGE2_SF_WORD5 STAGE2_SF_WORD6 STAGE2_SF_WORD7 STAGE2_SF_AMBIENT STAGE2_FF_AVG STAGE2_CDC_WORD0 STAGE2_CDC_WORD1 STAGE2_MAX_WORD0 STAGE2_MAX_WORD1 STAGE2_MAX_WORD2 STAGE2_MAX_WORD3 STAGE2_MAX_AVG STAGE2_HIGH_THRESHOLD STAGE2_MAX_TEMP STAGE2_MIN_WORD0 STAGE2_MIN_WORD1 STAGE2_MIN_WORD2 STAGE2_MIN_WORD3 STAGE2_MIN_AVG STAGE2_LOW_THRESHOLD STAGE2_MIN_TEMP Unused
AD7142/AD7142-1
Description STAGE2 CDC 16-Bit Conversion Data (Copy of data in STAGE2_CONV_DATA register) STAGE2 Fast FIFO WORD0 STAGE2 Fast FIFO WORD1 STAGE2 Fast FIFO WORD2 STAGE2 Fast FIFO WORD3 STAGE2 Fast FIFO WORD4 STAGE2 Fast FIFO WORD5 STAGE2 Fast FIFO WORD6 STAGE2 Fast FIFO WORD7 STAGE2 Slow FIFO WORD0 STAGE2 Slow FIFO WORD1 STAGE2 Slow FIFO WORD2 STAGE2 Slow FIFO WORD3 STAGE2 Slow FIFO WORD4 STAGE2 Slow FIFO WORD5 STAGE2 Slow FIFO WORD6 STAGE2 Slow FIFO WORD7 STAGE2 Slow FIFO Ambient Value STAGE2 Fast FIFO Average Value STAGE2 CDC FIFO WORD0 STAGE2 CDC FIFO WORD1 STAGE2 Maximum Value FIFO WORD0 STAGE2 Maximum Value FIFO WORD1 STAGE2 Maximum Value FIFO WORD2 STAGE2 Maximum Value FIFO WORD3 STAGE2 Average Maximum FIFO Value STAGE2 High Threshold Value STAGE2 Temporary Maximum Value STAGE2 Minimum Value FIFO WORD0 STAGE2 Minimum Value FIFO WORD1 STAGE2 Minimum Value FIFO WORD2 STAGE2 Minimum Value FIFO WORD3 STAGE2 Average Minimum FIFO Value STAGE2 Low Threshold Value STAGE2 Temporary Minimum Value
Rev. PrD | Page 49 of 64
AD7142/AD7142-1
Table 44. STAGE3 Results Register Map
Address 14C 14D 14E 14F 150 151 152 153 154 155 156 157 158 159 15A 15B 15C 15D 15E 15F 160 161 162 163 164 165 166 167 168 169 16A 16B 16C 16D 16E 16F Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE3_CONV_DATA STAGE3_FF_WORD0 STAGE3_FF_WORD1 STAGE3_FF_WORD2 STAGE3_FF_WORD3 STAGE3_FF_WORD4 STAGE3_FF_WORD5 STAGE3_FF_WORD6 STAGE3_FF_WORD7 STAGE3_SF_WORD0 STAGE3_SF_WORD1 STAGE3_SF_WORD2 STAGE3_SF_WORD3 STAGE3_SF_WORD4 STAGE3_SF_WORD5 STAGE3_SF_WORD6 STAGE3_SF_WORD7 STAGE3_SF_AMBIENT STAGE3_FF_AVG STAGE3_CDC_WORD0 STAGE3_CDC_WORD1 STAGE3_MAX_WORD0 STAGE3_MAX_WORD1 STAGE3_MAX_WORD2 STAGE3_MAX_WORD3 STAGE3_MAX_AVG STAGE3_HIGH_THRESHOLD STAGE3_MAX_TEMP STAGE3_MIN_WORD0 STAGE3_MIN_WORD1 STAGE3_MIN_WORD2 STAGE3_MIN_WORD3 STAGE3_MIN_AVG STAGE3_LOW_THRESHOLD STAGE3_MIN_TEMP Unused
Preliminary Technical Data
Description STAGE3 CDC 16-Bit Conversion Data (Copy of data in STAGE3_CONV_DATA register) STAGE3 Fast FIFO WORD0 STAGE3 Fast FIFO WORD1 STAGE3 Fast FIFO WORD2 STAGE3 Fast FIFO WORD3 STAGE3 Fast FIFO WORD4 STAGE3 Fast FIFO WORD5 STAGE3 Fast FIFO WORD6 STAGE3 Fast FIFO WORD7 STAGE3 Slow FIFO WORD0 STAGE3 Slow FIFO WORD1 STAGE3 Slow FIFO WORD2 STAGE3 Slow FIFO WORD3 STAGE3 Slow FIFO WORD4 STAGE3 Slow FIFO WORD5 STAGE3 Slow FIFO WORD6 STAGE3 Slow FIFO WORD7 STAGE3 Slow FIFO Ambient Value STAGE3 Fast FIFO Average Value STAGE3 CDC FIFO WORD0 STAGE3 CDC FIFO WORD1 STAGE3 Maximum Value FIFO WORD0 STAGE3 Maximum Value FIFO WORD1 STAGE3 Maximum Value FIFO WORD2 STAGE3 Maximum Value FIFO WORD3 STAGE3 Average Maximum FIFO Value STAGE3 High Threshold Value STAGE3 Temporary Maximum Value STAGE3 Minimum Value FIFO WORD0 STAGE3 Minimum Value FIFO WORD1 STAGE3 Minimum Value FIFO WORD2 STAGE3 Minimum Value FIFO WORD3 STAGE3 Average Minimum FIFO Value STAGE3 Low Threshold Value STAGE3 Temporary Minimum Value
Rev. PrD | Page 50 of 64
Preliminary Technical Data
Table 45. STAGE4 Results Register Map
Address 170 171 172 173 174 175 176 177 178 179 17A 17B 17C 17D 17E 17F 180 181 182 183 184 185 186 187 188 189 18A 18B 18C 18D 18E 18F 190 191 192 193 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE4_CONV_DATA STAGE4_FF_WORD0 STAGE4_FF_WORD1 STAGE4_FF_WORD2 STAGE4_FF_WORD3 STAGE4_FF_WORD4 STAGE4_FF_WORD5 STAGE4_FF_WORD6 STAGE4_FF_WORD7 STAGE4_SF_WORD0 STAGE4_SF_WORD1 STAGE4_SF_WORD2 STAGE4_SF_WORD3 STAGE4_SF_WORD4 STAGE4_SF_WORD5 STAGE4_SF_WORD6 STAGE4_SF_WORD7 STAGE4_SF_AMBIENT STAGE4_FF_AVG STAGE4_CDC_WORD0 STAGE4_CDC_WORD1 STAGE4_MAX_WORD0 STAGE4_MAX_WORD1 STAGE4_MAX_WORD2 STAGE4_MAX_WORD3 STAGE4_MAX_AVG STAGE4_HIGH_THRESHOLD STAGE4_MAX_TEMP STAGE4_MIN_WORD0 STAGE4_MIN_WORD1 STAGE4_MIN_WORD2 STAGE4_MIN_WORD3 STAGE4_MIN_AVG STAGE4_LOW_THRESHOLD STAGE4_MIN_TEMP Unused
AD7142/AD7142-1
Description STAGE4 CDC 16-Bit Conversion Data (Copy of data in STAGE4_CONV_DATA register) STAGE4 Fast FIFO WORD0 STAGE4 Fast FIFO WORD1 STAGE4 Fast FIFO WORD2 STAGE4 Fast FIFO WORD3 STAGE4 Fast FIFO WORD4 STAGE4 Fast FIFO WORD5 STAGE4 Fast FIFO WORD6 STAGE4 Fast FIFO WORD7 STAGE4 Slow FIFO WORD0 STAGE4 Slow FIFO WORD1 STAGE4 Slow FIFO WORD2 STAGE4 Slow FIFO WORD3 STAGE4 Slow FIFO WORD4 STAGE4 Slow FIFO WORD5 STAGE4 Slow FIFO WORD6 STAGE4 Slow FIFO WORD7 STAGE4 Slow FIFO Ambient Value STAGE4 Fast FIFO Average Value STAGE4 CDC FIFO WORD0 STAGE4 CDC FIFO WORD1 STAGE4 Maximum Value FIFO WORD0 STAGE4 Maximum Value FIFO WORD1 STAGE4 Maximum Value FIFO WORD2 STAGE4 Maximum Value FIFO WORD3 STAGE4 Average Maximum FIFO Value STAGE4 High Threshold Value STAGE4 Temporary Maximum Value STAGE4 Minimum Value FIFO WORD0 STAGE4 Minimum Value FIFO WORD1 STAGE4 Minimum Value FIFO WORD2 STAGE4 Minimum Value FIFO WORD3 STAGE4 Average Minimum FIFO Value STAGE4 Low Threshold Value STAGE4 Temporary Minimum Value
Rev. PrD | Page 51 of 64
AD7142/AD7142-1
Table 46. STAGE5 Results Register Map
Address 194 195 196 197 198 199 19A 19B 19C 19D 19E 19F 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1AA 1AB 1AC 1AD 1AE 1AF 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE5_CONV_DATA STAGE5_FF_WORD0 STAGE5_FF_WORD1 STAGE5_FF_WORD2 STAGE5_FF_WORD3 STAGE5_FF_WORD4 STAGE5_FF_WORD5 STAGE5_FF_WORD6 STAGE5_FF_WORD7 STAGE5_SF_WORD0 STAGE5_SF_WORD1 STAGE5_SF_WORD2 STAGE5_SF_WORD3 STAGE5_SF_WORD4 STAGE5_SF_WORD5 STAGE5_SF_WORD6 STAGE5_SF_WORD7 STAGE5_SF_AMBIENT STAGE5_FF_AVG STAGE5_CDC_WORD0 STAGE5_CDC_WORD1 STAGE5_MAX_WORD0 STAGE5_MAX_WORD1 STAGE5_MAX_WORD2 STAGE5_MAX_WORD3 STAGE5_MAX_AVG STAGE5_HIGH_THRESHOLD STAGE5_MAX_TEMP STAGE5_MIN_WORD0 STAGE5_MIN_WORD1 STAGE5_MIN_WORD2 STAGE5_MIN_WORD3 STAGE5_MIN_AVG STAGE5_LOW_THRESHOLD STAGE5_MIN_TEMP Unused
Preliminary Technical Data
Description STAGE5 CDC 16-Bit Conversion Data (Copy of data in STAGE5_CONV_DATA register) STAGE5 Fast FIFO WORD0 STAGE5 Fast FIFO WORD1 STAGE5 Fast FIFO WORD2 STAGE5 Fast FIFO WORD3 STAGE5 Fast FIFO WORD4 STAGE5 Fast FIFO WORD5 STAGE5 Fast FIFO WORD6 STAGE5 Fast FIFO WORD7 STAGE5 Slow FIFO WORD0 STAGE5 Slow FIFO WORD1 STAGE5 Slow FIFO WORD2 STAGE5 Slow FIFO WORD3 STAGE5 Slow FIFO WORD4 STAGE5 Slow FIFO WORD5 STAGE5 Slow FIFO WORD6 STAGE5 Slow FIFO WORD7 STAGE5 Slow FIFO Ambient Value STAGE5 Fast FIFO Average Value STAGE5 CDC FIFO WORD0 STAGE5 CDC FIFO WORD1 STAGE5 Maximum Value FIFO WORD0 STAGE5 Maximum Value FIFO WORD1 STAGE5 Maximum Value FIFO WORD2 STAGE5 Maximum Value FIFO WORD3 STAGE5 Average Maximum FIFO Value STAGE5 High Threshold Value STAGE5 Temporary Maximum Value STAGE5 Minimum Value FIFO WORD0 STAGE5 Minimum Value FIFO WORD1 STAGE5 Minimum Value FIFO WORD2 STAGE5 Minimum Value FIFO WORD3 STAGE5 Average Minimum FIFO Value STAGE5 Low Threshold Value STAGE5 Temporary Minimum Value
Rev. PrD | Page 52 of 64
Preliminary Technical Data
Table 47. STAGE6 Results Register Map
Address 1B8 1B9 1BA 1BB 1BC 1BD 1BE 1BF 1C0 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C9 1CA 1CB 1CC 1CD 1CE 1CF 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1DA 1DB Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE6_CONV_DATA STAGE6_FF_WORD0 STAGE6_FF_WORD1 STAGE6_FF_WORD2 STAGE6_FF_WORD3 STAGE6_FF_WORD4 STAGE6_FF_WORD5 STAGE6_FF_WORD6 STAGE6_FF_WORD7 STAGE6_SF_WORD0 STAGE6_SF_WORD1 STAGE6_SF_WORD2 STAGE6_SF_WORD3 STAGE6_SF_WORD4 STAGE6_SF_WORD5 STAGE6_SF_WORD6 STAGE6_SF_WORD7 STAGE6_SF_AMBIENT STAGE6_FF_AVG STAGE6_CDC_WORD0 STAGE6_CDC_WORD1 STAGE6_MAX_WORD0 STAGE6_MAX_WORD1 STAGE6_MAX_WORD2 STAGE6_MAX_WORD3 STAGE6_MAX_AVG STAGE6_HIGH_THRESHOLD STAGE6_MAX_TEMP STAGE6_MIN_WORD0 STAGE6_MIN_WORD1 STAGE6_MIN_WORD2 STAGE6_MIN_WORD3 STAGE6_MIN_AVG STAGE6_LOW_THRESHOLD STAGE6_MIN_TEMP Unused
AD7142/AD7142-1
Description STAGE6 CDC 16-Bit Conversion Data (Copy of data in STAGE6_CONV_DATA register) STAGE6 Fast FIFO WORD0 STAGE6 Fast FIFO WORD1 STAGE6 Fast FIFO WORD2 STAGE6 Fast FIFO WORD3 STAGE6 Fast FIFO WORD4 STAGE6 Fast FIFO WORD5 STAGE6 Fast FIFO WORD6 STAGE6 Fast FIFO WORD7 STAGE6 Slow FIFO WORD0 STAGE6 Slow FIFO WORD1 STAGE6 Slow FIFO WORD2 STAGE6 Slow FIFO WORD3 STAGE6 Slow FIFO WORD4 STAGE6 Slow FIFO WORD5 STAGE6 Slow FIFO WORD6 STAGE6 Slow FIFO WORD7 STAGE6 Slow FIFO Ambient Value STAGE6 Fast FIFO Average Value STAGE0 CDC FIFO WORD0 STAGE6 CDC FIFO WORD1 STAGE6 Maximum Value FIFO WORD0 STAGE6 Maximum Value FIFO WORD1 STAGE6 Maximum Value FIFO WORD2 STAGE6 Maximum Value FIFO WORD3 STAGE6 Average Maximum FIFO Value STAGE6 High Threshold Value STAGE6 Temporary Maximum Value STAGE6 Minimum Value FIFO WORD0 STAGE6 Minimum Value FIFO WORD1 STAGE6 Minimum Value FIFO WORD2 STAGE6 Minimum Value FIFO WORD3 STAGE6 Average Minimum FIFO Value STAGE6 Low Threshold Value STAGE6 Temporary Minimum Value
Rev. PrD | Page 53 of 64
AD7142/AD7142-1
Table 48. STAGE7 Results Register Map
Address 1DC 1DD 1DE 1DF 1E0 1E1 1E2 1E3 1E4 1E5 1E6 1E7 1E8 1E9 1EA 1EB 1EC 1ED 1EE 1EF 1F0 1F1 1F2 1F3 1F4 1F5 1F6 1F7 1F8 1F9 1FA 1FB 1FC 1FD 1FE 1FF Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE7_CONV_DATA STAGE7_FF_WORD0 STAGE7_FF_WORD1 STAGE7_FF_WORD2 STAGE7_FF_WORD3 STAGE7_FF_WORD4 STAGE7_FF_WORD5 STAGE7_FF_WORD6 STAGE7_FF_WORD7 STAGE7_SF_WORD0 STAGE7_SF_WORD1 STAGE7_SF_WORD2 STAGE7_SF_WORD3 STAGE7_SF_WORD4 STAGE7_SF_WORD5 STAGE7_SF_WORD6 STAGE7_SF_WORD7 STAGE7_SF_AMBIENT STAGE7_FF_AVG STAGE7_CDC_WORD0 STAGE7_CDC_WORD1 STAGE7_MAX_WORD0 STAGE7_MAX_WORD1 STAGE7_MAX_WORD2 STAGE7_MAX_WORD3 STAGE7_MAX_AVG STAGE7_HIGH_THRESHOLD STAGE7_MAX_TEMP STAGE7_MIN_WORD0 STAGE7_MIN_WORD1 STAGE7_MIN_WORD2 STAGE7_MIN_WORD3 STAGE7_MIN_AVG STAGE7_LOW_THRESHOLD STAGE7_MIN_TEMP Unused
Preliminary Technical Data
Description STAGE7 CDC 16-Bit Conversion Data (Copy of data in STAGE7_CONV_DATA register) STAGE7 Fast FIFO WORD0 STAGE7 Fast FIFO WORD1 STAGE7 Fast FIFO WORD2 STAGE7 Fast FIFO WORD3 STAGE7 Fast FIFO WORD4 STAGE7 Fast FIFO WORD5 STAGE7 Fast FIFO WORD6 STAGE7 Fast FIFO WORD7 STAGE7 Slow FIFO WORD0 STAGE7 Slow FIFO WORD1 STAGE7 Slow FIFO WORD2 STAGE7 Slow FIFO WORD3 STAGE7 Slow FIFO WORD4 STAGE7 Slow FIFO WORD5 STAGE7 Slow FIFO WORD6 STAGE7 Slow FIFO WORD7 STAGE7 Slow FIFO Ambient Value STAGE7 Fast FIFO Average Value STAGE7 CDC FIFO WORD0 STAGE7 CDC FIFO WORD1 STAGE7 Maximum Value FIFO WORD0 STAGE7 Maximum Value FIFO WORD1 STAGE7 Maximum Value FIFO WORD2 STAGE7 Maximum Value FIFO WORD3 STAGE7 Average Maximum FIFO Value STAGE7 High Threshold Value STAGE7 Temporary Maximum Value STAGE7 Minimum Value FIFO WORD0 STAGE7 Minimum Value FIFO WORD1 STAGE7 Minimum Value FIFO WORD2 STAGE7 Minimum Value FIFO WORD3 STAGE7 Average Minimum FIFO Value STAGE7 Low Threshold Value STAGE7 Temporary Minimum Value
Rev. PrD | Page 54 of 64
Preliminary Technical Data
Table 49. STAGE8 Results Register Map
Address 200 201 202 203 204 205 206 207 208 209 20A 20B 20C 20D 20E 20F 210 211 212 213 214 215 216 217 218 219 21A 21B 21C 21D 21E 21F 220 221 222 223 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE8_CONV_DATA STAGE8_FF_WORD0 STAGE8_FF_WORD1 STAGE8_FF_WORD2 STAGE8_FF_WORD3 STAGE8_FF_WORD4 STAGE8_FF_WORD5 STAGE8_FF_WORD6 STAGE8_FF_WORD7 STAGE8_SF_WORD0 STAGE8_SF_WORD1 STAGE8_SF_WORD2 STAGE8_SF_WORD3 STAGE8_SF_WORD4 STAGE8_SF_WORD5 STAGE8_SF_WORD6 STAGE8_SF_WORD7 STAGE8_SF_AMBIENT STAGE8_FF_AVG STAGE8_CDC_WORD0 STAGE8_CDC_WORD1 STAGE8_MAX_WORD0 STAGE8_MAX_WORD1 STAGE8_MAX_WORD2 STAGE8_MAX_WORD3 STAGE8_MAX_AVG STAGE8_HIGH_THRESHOLD STAGE8_MAX_TEMP STAGE8_MIN_WORD0 STAGE8_MIN_WORD1 STAGE8_MIN_WORD2 STAGE8_MIN_WORD3 STAGE8_MIN_AVG STAGE8_LOW_THRESHOLD STAGE8_MIN_TEMP Unused
AD7142/AD7142-1
Description STAGE8 CDC 16-Bit Conversion Data (Copy of data in STAGE8_CONV_DATA register) STAGE8 Fast FIFO WORD0 STAGE8 Fast FIFO WORD1 STAGE8 Fast FIFO WORD2 STAGE8 Fast FIFO WORD3 STAGE8 Fast FIFO WORD4 STAGE8 Fast FIFO WORD5 STAGE8 Fast FIFO WORD6 STAGE8 Fast FIFO WORD7 STAGE8 Slow FIFO WORD0 STAGE8 Slow FIFO WORD1 STAGE8 Slow FIFO WORD2 STAGE8 Slow FIFO WORD3 STAGE8 Slow FIFO WORD4 STAGE8 Slow FIFO WORD5 STAGE8 Slow FIFO WORD6 STAGE8 Slow FIFO WORD7 STAGE8 Slow FIFO Ambient Value STAGE8 Fast FIFO Average Value STAGE8 CDC FIFO WORD0 STAGE8 CDC FIFO WORD1 STAGE8 Maximum Value FIFO WORD0 STAGE8 Maximum Value FIFO WORD1 STAGE8 Maximum Value FIFO WORD2 STAGE8 Maximum Value FIFO WORD3 STAGE8 Average Maximum FIFO Value STAGE8 High Threshold Value STAGE8 Temporary Maximum Value STAGE8 Minimum Value FIFO WORD0 STAGE8 Minimum Value FIFO WORD1 STAGE8 Minimum Value FIFO WORD2 STAGE8 Minimum Value FIFO WORD3 STAGE8 Average Minimum FIFO Value STAGE8 Low Threshold Value STAGE7 Temporary Minimum Value
Rev. PrD | Page 55 of 64
AD7142/AD7142-1
Table 50. STAGE9 Results Register Map
Address 224 225 226 227 228 229 22A 22B 22C 22D 22E 22F 230 231 232 233 234 235 236 237 238 239 23A 23B 23C 23D 23E 23F 240 241 242 243 244 245 246 247 Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE9_CONV_DATA STAGE9_FF_WORD0 STAGE9_FF_WORD1 STAGE9_FF_WORD2 STAGE9_FF_WORD3 STAGE9_FF_WORD4 STAGE9_FF_WORD5 STAGE9_FF_WORD6 STAGE9_FF_WORD7 STAGE9_SF_WORD0 STAGE9_SF_WORD1 STAGE9_SF_WORD2 STAGE9_SF_WORD3 STAGE9_SF_WORD4 STAGE9_SF_WORD5 STAGE9_SF_WORD6 STAGE9_SF_WORD7 STAGE9_SF_AMBIENT STAGE9_FF_AVG STAGE9_CDC_WORD0 STAGE9_CDC_WORD1 STAGE9_MAX_WORD0 STAGE9_MAX_WORD1 STAGE9_MAX_WORD2 STAGE9_MAX_WORD3 STAGE9_MAX_AVG STAGE9_HIGH_THRESHOLD STAGE9_MAX_TEMP STAGE9_MIN_WORD0 STAGE9_MIN_WORD1 STAGE9_MIN_WORD2 STAGE9_MIN_WORD3 STAGE9_MIN_AVG STAGE9_LOW_THRESHOLD STAGE9_MIN_TEMP Unused
Preliminary Technical Data
Description STAGE9 CDC 16-Bit Conversion Data (Copy of data in STAGE9_CONV_DATA register) STAGE9 Fast FIFO WORD0 STAGE9 Fast FIFO WORD1 STAGE9 Fast FIFO WORD2 STAGE9 Fast FIFO WORD3 STAGE9 Fast FIFO WORD4 STAGE9 Fast FIFO WORD5 STAGE9 Fast FIFO WORD6 STAGE9 Fast FIFO WORD7 STAGE9 Slow FIFO WORD0 STAGE9 Slow FIFO WORD1 STAGE9 Slow FIFO WORD2 STAGE9 Slow FIFO WORD3 STAGE9 Slow FIFO WORD4 STAGE9 Slow FIFO WORD5 STAGE9 Slow FIFO WORD6 STAGE9 Slow FIFO WORD7 STAGE9 Slow FIFO Ambient Value STAGE9 Fast FIFO Average Value STAGE9 CDC FIFO WORD0 STAGE9 CDC FIFO WORD1 STAGE9 Maximum Value FIFO WORD0 STAGE9 Maximum Value FIFO WORD1 STAGE9 Maximum Value FIFO WORD2 STAGE9 Maximum Value FIFO WORD3 STAGE9 Average Maximum FIFO Value STAGE9 High Threshold Value STAGE9 Temporary Maximum Value STAGE9 Minimum Value FIFO WORD0 STAGE9 Minimum Value FIFO WORD1 STAGE9 Minimum Value FIFO WORD2 STAGE9 Minimum Value FIFO WORD3 STAGE9 Average Minimum FIFO Value STAGE9 Low Threshold Value STAGE9 Temporary Minimum Value
Rev. PrD | Page 56 of 64
Preliminary Technical Data
Table 51. STAGE10 Results Register Map
Address 248 249 24A 24B 24C 24D 24E 24F 250 251 252 253 254 255 256 257 258 259 25A 25B 25C 25D 25E 25F 260 261 262 263 264 265 266 267 268 269 26A 26B Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE10_CONV_DATA STAGE10_FF_WORD0 STAGE10_FF_WORD1 STAGE10_FF_WORD2 STAGE10_FF_WORD3 STAGE10_FF_WORD4 STAGE10_FF_WORD5 STAGE10_FF_WORD6 STAGE10_FF_WORD7 STAGE10_SF_WORD0 STAGE10_SF_WORD1 STAGE10_SF_WORD2 STAGE10_SF_WORD3 STAGE10_SF_WORD4 STAGE10_SF_WORD5 STAGE10_SF_WORD6 STAGE10_SF_WORD7 STAGE10_SF_AMBIENT STAGE10_FF_AVG STAGE10_CDC_WORD0 STAGE10_CDC_WORD1 STAGE10_MAX_WORD0 STAGE10_MAX_WORD1 STAGE10_MAX_WORD2 STAGE10_MAX_WORD3 STAGE10_MAX_AVG STAGE10_HIGH_THRESHOLD STAGE10_MAX_TEMP STAGE10_MIN_WORD0 STAGE10_MIN_WORD1 STAGE10_MIN_WORD2 STAGE10_MIN_WORD3 STAGE10_MIN_AVG STAGE10_LOW_THRESHOLD STAGE10_MIN_TEMP Unused
AD7142/AD7142-1
Description STAGE10 CDC 16-Bit Conversion Data (Copy of data in STAGE10_CONV_DATA register) STAGE10 Fast FIFO WORD0 STAGE10 Fast FIFO WORD1 STAGE10 Fast FIFO WORD2 STAGE10 Fast FIFO WORD3 STAGE10 Fast FIFO WORD4 STAGE10 Fast FIFO WORD5 STAGE10 Fast FIFO WORD6 STAGE10 Fast FIFO WORD7 STAGE10 Slow FIFO WORD0 STAGE10 Slow FIFO WORD1 STAGE10 Slow FIFO WORD2 STAGE10 Slow FIFO WORD3 STAGE10 Slow FIFO WORD4 STAGE10 Slow FIFO WORD5 STAGE10 Slow FIFO WORD6 STAGE10 Slow FIFO WORD7 STAGE10 Slow FIFO Ambient Value STAGE10 Fast FIFO Average Value STAGE10 CDC FIFO WORD0 STAGE10 CDC FIFO WORD1 STAGE10 Maximum Value FIFO WORD0 STAGE10 Maximum Value FIFO WORD1 STAGE10 Maximum Value FIFO WORD2 STAGE10 Maximum Value FIFO WORD3 STAGE10 Average Maximum FIFO Value STAGE10 High Threshold Value STAGE10 Temporary Maximum Value STAGE10 Minimum Value FIFO WORD0 STAGE10 Minimum Value FIFO WORD1 STAGE10 Minimum Value FIFO WORD2 STAGE10 Minimum Value FIFO WORD3 STAGE10 Average Minimum FIFO Value STAGE10 Low Threshold Value STAGE10 Temporary Minimum Value
Rev. PrD | Page 57 of 64
AD7142/AD7142-1
Table 52. STAGE11 Results Register Map
Address 26C 26D 26E 26F 270 271 272 273 274 275 276 277 278 279 27A 27B 27C 27D 27E 27F 280 281 282 283 284 285 286 287 288 289 28A 28B 28C 28D 28E 28F Data Bit Content [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Default Value X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Name STAGE11_CONV_DATA STAGE11_FF_WORD0 STAGE11_FF_WORD1 STAGE11_FF_WORD2 STAGE11_FF_WORD3 STAGE11_FF_WORD4 STAGE11_FF_WORD5 STAGE11_FF_WORD6 STAGE11_FF_WORD7 STAGE11_SF_WORD0 STAGE11_SF_WORD1 STAGE11_SF_WORD2 STAGE11_SF_WORD3 STAGE11_SF_WORD4 STAGE11_SF_WORD5 STAGE11_SF_WORD6 STAGE11_SF_WORD7 STAGE11_SF_AMBIENT STAGE11_FF_AVG STAGE11_CDC_WORD0 STAGE11_CDC_WORD1 STAGE11_MAX_WORD0 STAGE11_MAX_WORD1 STAGE11_MAX_WORD2 STAGE11_MAX_WORD3 STAGE11_MAX_AVG STAGE11_HIGH_THRESHOLD STAGE11_MAX_TEMP STAGE11_MIN_WORD0 STAGE11_MIN_WORD1 STAGE11_MIN_WORD2 STAGE11_MIN_WORD3 STAGE11_MIN_AVG STAGE11_LOW_THRESHOLD STAGE11_MIN_TEMP Unused
Preliminary Technical Data
Description STAGE11 CDC 16-Bit Conversion Data (Copy of data in STAGE11_CONV_DATA register) STAGE11 Fast FIFO WORD0 STAGE11 Fast FIFO WORD1 STAGE11 Fast FIFO WORD2 STAGE11 Fast FIFO WORD3 STAGE11 Fast FIFO WORD4 STAGE11 Fast FIFO WORD5 STAGE11 Fast FIFO WORD6 STAGE11 Fast FIFO WORD7 STAGE11 Slow FIFO WORD0 STAGE11 Slow FIFO WORD1 STAGE11 Slow FIFO WORD2 STAGE11 Slow FIFO WORD3 STAGE11 Slow FIFO WORD4 STAGE11 Slow FIFO WORD5 STAGE11 Slow FIFO WORD6 STAGE11 Slow FIFO WORD7 STAGE11 Slow FIFO Ambient Value STAGE11 Fast FIFO Average Value STAGE11 CDC FIFO WORD0 STAGE11 CDC FIFO WORD1 STAGE11 Maximum Value FIFO WORD0 STAGE11 Maximum Value FIFO WORD1 STAGE11 Maximum Value FIFO WORD2 STAGE11 Maximum Value FIFO WORD3 STAGE11 Average Maximum FIFO Value STAGE11 High Threshold Value STAGE11 Temporary Maximum Value STAGE11 Minimum Value FIFO WORD0 STAGE11 Minimum Value FIFO WORD1 STAGE11 Minimum Value FIFO WORD2 STAGE11 Minimum Value FIFO WORD3 STAGE11 Average Minimum FIFO Value STAGE11 Low Threshold Value STAGE11 Temporary Minimum Value
Rev. PrD | Page 58 of 64
Preliminary Technical Data
Table 53. STAGEX Detailed CIN (0:6) Connection Setup Description (X = 0 to 11)
Data Bit Content [1:0] Default Value X Type R/W Name CIN0_CONNECTION_SETUP
AD7142/AD7142-1
Description CIN0 Connection Setup 00 = CIN0 not connected to CDC inputs 01 = CIN0 connected to CDC negative input 10 = CIN0 connected to CDC positive input 11 = CIN0 connected to BIAS (connect unused CIN inputs) CIN1 Connection Setup 00 = CIN1 not connected to CDC inputs 01 = CIN1 connected to CDC negative input 10 = CIN1 connected to CDC positive input 11 = CIN1 connected to BIAS (connect unused CIN inputs) CIN2 Connection Setup 00 = CIN2 not connected to CDC inputs 01 = CIN2 connected to CDC negative input 10 = CIN2 connected to CDC positive input 11 = CIN2 connected to BIAS (connect unused CIN inputs) CIN3 Connection Setup 00 = CIN3 not connected to CDC inputs 01 = CIN3 connected to CDC negative input 10 = CIN3 connected to CDC positive input 11 = CIN3 connected to BIAS (connect unused CIN inputs) CIN4 Connection Set-Up 00 = CIN4 not connected to CDC inputs 01 = CIN4 connected to CDC negative input 10 = CIN4 connected to CDC positive input 11 = CIN4 connected to BIAS (connect unused CIN inputs) CIN5 Connection Setup 00 = CIN5 not connected to CDC inputs 01 = CIN5 connected to CDC negative input 10 = CIN5 connected to CDC positive input 11 = CIN5 connected to BIAS (connect unused CIN inputs) CIN6 Connection Setup 00 = CIN6 not connected to CDC inputs 01 = CIN6 connected to CDC negative input 10 = CIN6 connected to CDC positive input 11 = CIN6 connected to BIAS (connect unused CIN inputs)
[3:2]
X
R/W
CIN1_CONNECTION_SETUP
[5:4]
X
R/W
CIN2_CONNECTION_SETUP
[7:6]
X
R/W
CIN3_CONNECTION_SETUP
[9:8]
X
R/W
CIN4_CONNECTION_SETUP
[11:10]
X
R/W
CIN5_CONNECTION_SETUP
[13:12]
X
R/W
CIN6_CONNECTION_SETUP
[15:14]
X
Unused
Rev. PrD | Page 59 of 64
AD7142/AD7142-1
Table 54. STAGEX Detailed CIN (7:13) Connection Setup Description (X = 0 to 11)
Data Bit Content [1:0] Default Value X Type R/W Name CIN7_CONNECTION_SETUP
Preliminary Technical Data
Description CIN7 Connection Setup 00 = CIN7 not connected to CDC inputs 01 = CIN7 connected to CDC negative input 10 = CIN7 connected to CDC positive input 11 = CIN7 connected to BIAS (connect unused CIN inputs) CIN8 Connection Setup 00 = CIN8 not connected to CDC inputs 01 = CIN8 connected to CDC negative input 10 = CIN8 connected to CDC positive input 11 = CIN8 connected to BIAS (connect unused CIN inputs) CIN9 Connection Set-Up 00 = CIN9 not connected to CDC inputs 01 = CIN9 connected to CDC negative input 10 = CIN9 connected to CDC positive input 11 = CIN9 connected to BIAS (connect unused CIN inputs) CIN10 Connection Setup 00 = CIN10 not connected to CDC inputs 01 = CIN10 connected to CDC negative input 10 = CIN10 connected to CDC positive input 11 = CIN10 connected to BIAS (connect unused CIN inputs) CIN11 Connection Setup 00 = CIN11 not connected to CDC inputs 01 = CIN11 connected to CDC negative input 10 = CIN11 connected to CDC positive input 11 = CIN11 connected to BIAS (connect unused CIN inputs) CIN12 Connection Setup 00 = CIN12 not connected to CDC inputs 01 = CIN12 connected to CDC negative input 10 = CIN12 connected to CDC positive input 11 = CIN12 connected to BIAS (connect unused CIN inputs) CIN13 Connection Setup 00 = CIN13 not connected to CDC inputs 01 = CIN13 connected to CDC negative input 10 = CIN13 connected to CDC positive input 11 = CIN13 connected to BIAS (connect unused CIN inputs) Negative AFE Offset Enable Control 0 = enable 1 = disable Positive AFE offset Enable Control 0 = enable 1 = disable
[3:2]
X
R/W
CIN8_CONNECTION_SETUP
[5:4]
X
R/W
CIN9_CONNECTION_SETUP
[7:6]
X
R/W
CIN10_CONNECTION_SETUP
[9:8]
X
R/W
CIN11_CONNECTION_SETUP
[11:10]
X
R/W
CIN12_CONNECTION_SETUP
[13:12]
X
R/W
CIN13_CONNECTION_SETUP
[14]
X
NEG_AFE_OFFSET_DISABLE
[15]
X
POS_AFE_OFFSET_DISABLE
Rev. PrD | Page 60 of 64
Preliminary Technical Data
Table 55. STAGEX Detailed Offset Control Description (X = 0 to 11)
Data Bit Content [6:0] [7] Default Value X X Type R/W R/W Name NEG_AFE_OFFSET NEG_AFE_OFFSET_SWAP
AD7142/AD7142-1
Description Negative AFE Offset Setting (20 pF Range) 1 LSB value = 0.16 pF of offset Negative AFE Offset Swap Control 0 = NEG_AFE_OFFSET applied to CDC negative input 1 = NEG_AFE_OFFSET applied to CDC positive input Positive AFE Offset Setting (20 pF Range) 1 LSB value = 0.16 pF of offset Positive AFE Offset Swap Control 0 = POS_AFE_OFFSET applied to CDC positive input 1 = POS_AFE_OFFSET applied to CDC negative input
[14:8] [15]
X X
R/W R/W
POS_AFE_OFFSET POS_AFE_OFFSET_SWAP
Table 56. STAGEX Detailed Sensitivity Control Description (X = 0 to 11)
Data Bit Content [3:0] Default Value X Type R/W Name NEG_THRESHOLD_SENSITIVITY Description Negative Threshold Sensitivity Control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% Negative Peak Detect Setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% Level, 101 = 90% level Positive Threshold Sensitivity Control 0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08% 0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15% 0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22% 1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28% 1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32% Positive Peak Detect Setting 000 = 40% level, 001 = 50% level, 010 = 60% level 011 = 70% level, 100 = 80% level, 101 = 90% level
[6:4]
X
R/W
NEG_PEAK_DETECT
[7] [11:8]
X X
R/W R/W
Unused POS_THRESHOLD_SENSITIVITY
[14:12]
X
R/W
POS_PEAK_DETECT
[15]
X
R/W
Unused
Rev. PrD | Page 61 of 64
AD7142/AD7142-1 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24
Preliminary Technical Data
PIN 1 INDICATOR
32 1
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30
9
0.25 MIN 3.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 48. 32-Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Very Thin Quad (CP-32-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7142ACPZ-REEL 1 AD7142ACPZ-REEL71 AD7142-1ACPZ-REEL1 AD7142-1ACPZ-REEL71 Eval-AD7142EB Eval-AD7142EB-1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to +85C 0C to +85C
Serial Interface Description SPI Interface SPI Interface I2C Interface I2C Interface SPI Interface I2C Interface
Package Description 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP Evaluation Board Evaluation Board
Package Option CP-32-3 CP-32-3 CP-32-3 CP-32-3
Z = Pb-free part.
Rev. PrD | Page 62 of 64
Preliminary Technical Data NOTES
AD7142/AD7142-1
Rev. PrD | Page 63 of 64
AD7142/AD7142-1 NOTES
Preliminary Technical Data
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05702-0-12/05(PrD)
Rev. PrD | Page 64 of 64

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